Issue link: https://iconnect007.uberflip.com/i/1464168
APRIL 2022 I DESIGN007 MAGAZINE 39 semi-additive environment, this is not the case. ere are a couple things to consider. First, on innerlayers, this spacing could be 25 microns or below, depending on the technology being used by the PCB fabricator. Outerlayers need to take solder mask into consideration. ere needs to be enough space to allow the solder mask to fully cover the trace and not expose any copper. e thickness of copper typically determines how far you need to be away from the pad. A good rule of thumb would be to use a 50-micron gap. What do I need to know to meet a 50-ohm impedance? First, this topic will be addressed in a future column in much more detail. But I will tease a few high-level tips here. First, be sure that the modeling tool you are using is set for straight sidewalls if you are working with a fabrica- tor offering A-SAP. is does have an impact. Second, pay close attention to copper height. Narrow traces will have higher loss, which is a fact, but decreasing dielectric thickness and increasing copper height do mitigate that. e ability to fabricate high aspect ratio traces (taller than wide) is dependent on the SAP technology used, so be sure to work with your fabricator as your PCB design develops. ere is a lot of work being done to help educate PCB designers about this new tech- nology. is is our opportunity to design with manufacturing and to creatively approach these new capabilities both from a fabrica- tion perspective and a design perspective. We will continue to dive into this in future col- umns, but please contact me with any burning questions. DESIGN007 Tara Dunn is the vice president of marketing and business development for Averatek. To read past columns or contact Dunn, click here. In an earlier column, "Bridging the Gap Between Design and Analysis with In-Design Analysis," Brad Griffin discussed how the "shift left" that's happening with electronic design means it is no longer sufficient for signal integrity (SI) and power integrity (PI) analysis to be performed in isolation. Designing, analyzing, and verifying the design in its entirety is key. Another facet of this shift left is the need to address thermal integrity (TI) sooner rather than later. In other words, find- ing and fixing thermal PCB design issues early in the design process is necessary to save costs, reduce design spins, and maintain your own sanity. Electrothermal co-simulation—understanding the implications (intended or otherwise) of ther- mal interactions on electrical performance for high-speed (or high-frequency) PCB designs—is now essential for successful end-product devel- opment. Let's start by looking at things from the highest level, which is that we want to design a PCB. At some stage, this PCB (possibly accompanied by one or more additional PCBs) will be mounted in an enclosure. Eventually, this system will be deployed into the field. The designers of the PCB(s) and the system as a whole want to know how well the system will perform and how long it will survive. To read the entire column, click here. All Systems Go! Find and Fix Thermal PCB Problems Sooner Than Later by Melika Roshandell CADENCE