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50 The PCB Design Magazine • March 2016 ing, within an expected life span of three years (26208 hours) this means approximately three decades of time, resulting in a -7.5% capaci- tance drop. If we consider the worst-case cumu- lative effect of all of the above contributors, we need to multiply all of the ratios corresponding to these percentage values. In the table below, we repeat the list of contributors together with their worst-case limits for the example part. When we multiply the worst-case contrib- utors, we get 0.9*0.85*0.3*0.7*0.925 = 0.15, which means instead of 1uF we have only 0.15uF capacitance. From the table we also see that with modern high density ceramic capaci- tors the biggest possible capacitance drop is due to the DC and AC bias effects. In some ap- plications the loss of capacitance is important to know and therefore users want to simulate it. Until recently, however, simulation models were available only for no-bias conditions. This has changed with the emerging dy- namic models [4] , which use controlled sources inside encrypted models to create a true non- linear response according to the instantaneous excitation across the part. Dynamic models are currently available for a number of popular simulators. The examples shown here were run on Linear Technologies LTSPICE. For the illus- trations below we use a GRM219R60G476ME44 part, which is 47uF +-20% X5R 4V capacitor in a 0805-size package. Figure 2 shows the LTSPICE circuit to simulate the impedance of the capaci- tor with different bias conditions and Figure 3 shows the impedance with 4V DC bias. The data from Figure 3 can be post processed and we can display impedance magnitude and dynamic models for passiVe components Table 1. Figure 2: LTSPICE simulation deck to calculate the linearized impedance at the 4V DC bias point. Figure 3: Impedance versus frequency (magnitude, solid line, left axis and phase, dashed line, right axis) of the GRM- 219R60G476ME44 capacitor, simulated with its dynamic model.

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