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60 DESIGN007 MAGAZINE I DECEMBER 2018 for adding the redistribution layer (RDL), the fabricator will first sputter-coat a metal alloy adhesion layer onto the wafers active surface. Adhesion-promoting metals include nickel (Ni), molybdenum (Mo), chrome (Cr), tung- sten (W), and titanium (Ti). Resist is applied over the wafer's surface and photo-imaged to delineate the interconnect pattern and com- ponent termination sites (land patterns). The wafer(s) is then made ready for the electroplat- ing process, building up additional metal over the exposed RDL pattern. Copper has become the preferred alloy for RDL circuit plating. Following pattern plating, the resist coat- ing is removed, and the remaining thin adhe- sion layer metalization is chemically etched from the silicon surface, leaving only the interconnect pattern and terminal lands. After cleaning, a photo-imaged passivation layer is applied to define the termination pattern and insulate and protect the conductive circuit pattern. The general RDL process sequence is shown in Figure 1. Further plating or coating processes may be applied to prevent oxidation of the exposed bare-copper terminal surfaces. Wafer Thinning Silicon wafers are furnished in diameters ranging from approximately 50–400 mm with a thickness range of 280–775 μm. Following the metalization (RDL) process, the wafers are commonly subjected to backside thinning and polishing. To prepare for thinning, the wafer is placed in a vacuum chuck with the active surface down and processed on the backside surface using both coarse and fine-grinding steps to reduce wafer thickness. Dry polish- ing follows to achieve the desired surface fin- ish, ensure stress relief, and provide a degree of strength for the thin and somewhat frag- ile wafers. The preferred finished thickness of the semiconductor die element prepared for embedding will be between 130–150 μm (0.005–0.006"). Singulation Process Saw dicing is widely employed for separat- ing the individual semiconductor die elements from the wafer-level format. For low-volume or moderately varied processing, wafers are first mounted onto a UV tape-based film furnished on a tape frame (ring). Conventional dicing usu - ally utilizes high-precision diamond enriched resin-bonded saw blades mounted onto high- speed spindles to cut through the silicon. A typical problem associated with controlling sawing accuracy of the semiconductor wafer is mechanical deformation or substrate warpage. To minimize material distortion during the saw process, high-pressure water nozzles flood the workpiece and blade to provide cooling. The blades used in conventional dicing saws vary in size depending on the material thick- ness and "saw-street" width, which is the distance between the outer edge of each die on a wafer or panel. Blade selection is highly dependent upon street width. Material thick- ness plays a critical role in blade selection as well; thick materials require wider blades to provide adequate blade strength. As the blade Figure 1: Basic RDL pattern imaging, plating, and etching process sequence.

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