Issue link: https://iconnect007.uberflip.com/i/1071356
42 DESIGN007 MAGAZINE I JANUARY 2019 reality, data transmission is imperfect, so the transitions of the bit pattern do not perfectly align on top of each other, and an eye-shaped pattern results. An open-eye pattern with little jitter (horizontal disparity) and noise (vertical deviation) is the objective. To attain this objective one needs to consider all the previous fundamental rules particularly: • Control the impedance. • Match the driver to the transmission line impedance. • Tightly couple all signal traces to a contiguous reference plane and have a clearly defined minimum loop inductance return current path. • Maintain constant impedance along the entire length of differential pairs. • Synchronous data and address buses, plus associated clocks and strobes, should have matched propagation within their timing margin. A preliminary batch mode simulation should initially be completed on the design. Default IC characteristics, crosstalk of 150mV maximum and EMC to FCC or CISPR Class A and B, are set up in the simulator. The batch mode simulation automatically scans large numbers of nets on an entire PCB, flagging signal integrity, crosstalk, and EMC hot spots. The post-layout simulation analysis can then be prepared using supplied specifications. This is an extensive interactive board level simulation which takes the analysis to the next level–simulating trouble spots identified by the batch analysis to further resolve the issues with greater accuracy. Keep in mind that any signal integrity concern will create issues downstream with ringing causing excessive crosstalk leading to electromagnetic radiation. Each issue should be dealt with one-by-one until they are all resolved. Flight times of the critical signals should be examined thoroughly. One could compare the matched lengths of each signal, but the delay will vary depending on the meander pattern and the signal layer in the stackup. Also, the trace either side of a series terminator needs to be added to obtain the total delay. So instead, Figure 2: Eye diagram indicating signal quality (Figures 2–6 simulated in HyperLynx).