Issue link: https://iconnect007.uberflip.com/i/1071356
JANUARY 2019 I DESIGN007 MAGAZINE 59 Gold-on-gold Termination Raised gold bump terminals are formed on each bond site utilizing the same basic system developed for wire-bond assembly. The actual die attachment technique utilizes heat, pressure, and ultrasonic or thermosonic energy to form a welded interconnection from the gold-bumped die to the substrate's gold- on-copper land pattern. Furthermore, the GGI process eliminates the need for applying flux and cleaning before dispensing underfill and applying the prepreg laminate or RCC material . Microvia Semiconductor Termination When the die is mounted with the active surface facing away from the substrate surface, interconnect between die and substrate can rely on copper-plated microvia termination. In preparation for microvia termination, the termination sites on the semiconductor must be furnished with a copper surface. Following the placement and lamination encapsulating the die element, laser systems are employed to ablate material at each terminal site followed by a sequence of plating, imaging, and etching processes (Figure 3) to complete the interface from the die to the buildup circuit layer. Microvia interface methodology is favored by a growing number of companies because they can eliminate several process steps: material dispensing, thermal curing or reflow processing, cleaning, and underfill application. Although the core mounted-semiconductor element is a popular technique for embedding active die, a number of innovative coreless embedding methodologies have evolved as well. Die-first Coreless Process Developed in Europe with a consortium of the industry and academia, a die-first assembly method adopts a variation of the Occam process for embedding and interconnecting semiconductor die elements. The process begins with laser marking fiducial targets on the surface of an ultra-thin copper foil base layer (Figure 4). A pattern of adhesive material that is slightly larger than the semiconductor outline is printed onto the copper surface and partially cured to furnish a stable surface for device attachment. Figure 3: Microvia-to-faceup-semiconductor interface process sequence.