Issue link: https://iconnect007.uberflip.com/i/1114420
MAY 2019 I DESIGN007 MAGAZINE 41 come into play. If you define rules for every single signal, you're going to spend your life defining the constraints. Again, that brings in the hierarchy, and ways to define rules ripple down to define a high-level constraint that's applied to a whole bunch of nets. If you need to tweak individual nets within a bunch of one hundred, for instance, you can do that. But you don't want to have to individually define the constraint for every one of them, and then find out that you messed something up and have to go back to all of them. Shaughnessy: So many of these things are on the edge. Some fabricators say that they re- ceive boards that are listed as Class 2, but they push it so much that they call it Class 2.5. Wiens: Yes. How can we do it cost-effectively is the other side? And from a performance per- spective, you can over-constrain a design. You can say, "I need an extra 10 layers to shield all of the signals," but that's not cost-effective, and the only way to determine the appropriate constraints is to run an analysis up front. How loose can you make the constraints so that you can still achieve the performance you're look- ing for at the cost target? Shaughnessy: That's what your co-worker Todd Westerhoff once said: "What's the dirti- est I can make my signal and have it still work (laughs)?" Wiens: Exactly. In this case, being a purist is easy. I want my digital signal to look like digi- tal signals. You have to have some degree of at- tenuation or noisiness on the signal; that's go- ing to happen. Shaughnessy: From what I've seen with the IC world, it seems like they solved the design rule problem 20 years ago in their segment. I guess it was out of necessity because if you have a re-spin of a chip, that costs hundreds of thou- sands of dollars. Plus, there were only a hand- ful of foundries compared to the number of PCB fabricators, so it would be simpler to set up manufacturing rules, right? Wiens: I'm not an IC expert by any means, and I'll let Mike speak to that, but I can tell you a few things that they've hit. Number one, the IC vendors hammered home the golden verifier approach. They said, "We're not going to even accept a design from you unless we know that you adhere to these rules. There's no point be- cause of the cost associated with it." And that concept that everybody has to validate some- thing using one tool drove those rules into the design process. You had to use those rules. Another thing they did was go to a block- based design approach that said there are reus- able blocks of IP from one design to the next. First, it gives you immediate quality. You de- signed and verified that IP once, so it's a known good IP. Second, it accelerates the design pro- cess because you're reusing stuff—not just re- doing stuff. Now, the idea of buying IP from somebody else and reusing it hasn't caught on with the PCB side, but it has with the IC side. Synopsys has made good money off of that. Do you have anything to add from an IC perspec- tive, Mike? Mike Santarini: Another thing in the IC space is that fewer companies are man- ufacturing the chips now. Silicon foundries have more control of their par- ticular processes because they make their mon- ey by producing massive amounts of silicon and getting a good yield. The goal is to get it right the first time. At some point, they tell custom- ers, "This is what the process is. You must use this vendor's specific tool to ensure that what you've designed conforms to what will be manufactured." The other thing is all of the equipment; they standardize on the kind of equipment they're going to use at each process node. What does it look like in the PCB space, Dave? Are there still a lot of people mixing and matching what equipment they use? Wiens: Absolutely. There are many more man- ufacturers and a lot of variability in equip- Mike Santarini