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56 DESIGN007 MAGAZINE I JULY 2019 terconnection inductance in Equations 3 and 4, it is crucial to keep the interconnection in- ductance low to minimize the impedance of the PDN, which is achievable by reducing trace length and stitching via height. Equation 1: • L = parasitic inductance of stitching via (unit nH) • h = stitching via height (unit mm) • d = via hole diameter (unit mm) Equation 2: • L = parasitic inductance of inter- connection trace (unit nH) • l = trace length (cm) • w = trace width (cm) • h = dielectric substrate thickness (cm) • t = trace thickness (cm) Equation 3: Equation 4: • X L = inductive reactance (unit ohm) • Z = impedance (unit ohm) • f = frequency (unit GHz) • L = interconnection inductance (nH) The analysis of the impact of interconnec- tion inductance due to stitching via height and trace length is discussed in section A and B, re- spectively, in this article. A. Impact of Stitching Via Height To investigate the impact of interconnec- tion inductance due to stitching via height on the impedance of decoupling capacitor, three simulation models are constructed using Key- sight EMPro. In model 1A (Figure 2), a 0201 package decoupling capacitor with two termi- nal pads separated 10 mils apart (10 mils by 5 mils per pad) is constructed. This 0.1-uF ca- pacitor is set to have an intrinsic parasitic ESR of 0.005 ohms and an ESL of 0.5 nH. One of its terminal pads is connected to the middle of a 50-mil fixture trace (representing the pow - er rail) with trace length, l, of 20 mils. Mean- while, its second terminal pad is hooked up to the ground plane on layer 2 of the PCB with trace length, l, of 20 mils and stitching via height, h, of 2.65 mils. The 1-oz. top layer of copper is separated from the ground plane on layer 2 using low-loss dielectric material also with a height, h, of 2.65 mils. Subsequently, two-port shunt probing points are positioned Figure 2: 3DEM structure of model 1A together with 50-mil fixture trace.

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