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22 DESIGN007 MAGAZINE I JULY 2020 In a previous column on "Transmission Line Terminations," I discussed the three most common termination strategies: series, end, and differential. These techniques are used to eliminate impedance mismatch and hence reflections to avoid crosstalk and electromag- netic radiation. As a general rule, transmission line (trace) termination is necessary when the round trip propagation time of the signal is equal to or greater than the transition (rise or fall) time of the driver; otherwise, there will be data errors caused by signal degradation. In this month's column, I will elaborate on two particular cases of series termination that every PCB designer will come across. 1. Distributing a Clock to Multiple Loads The objective of the clock is to provide cir- cuit timing and thereby coordinate the activity within the system. With memory circuits, the clock pulse will trigger the input and output of Alternative Series Termination Techniques data, and therefore, must be timed such that each bit of data arrives and stabilizes before the next clock cycle. To do this means that both the clock and data lines must be routed to exact delays within the specified setup and hold times. Since digital signals cannot be sped up, the only option is to add length to the line to delay the signal arrival to match the arrival speed of the longest lines in the bus. However, the clock signal should always be the longest delay of all so that the data signals have time to settle before they are clocked. Routing clock signals to multiple loads can be done in many ways. A buffer could be used for each individual receiver, or the use of a dedicated clock driver incorporating a phase- locked loop (PPL) to synchronize the timing is also a common solution. However, this adds to the cost and consumes precious real estate. Star routing is ideal for distributing a clock to multiple loads in low- to medium-speed Beyond Design by Barry Olney, IN-CIRCUIT DESIGN PTY LTD / AUSTRALIA