Issue link: https://iconnect007.uberflip.com/i/1299286
OCTOBER 2020 I PCB007 MAGAZINE 61 cleaning out and defining the spaces between the lines. SAP allows for finer lines and spac- es than mSAP primarily since it requires fewer additive steps of copper plating and less etch- ing to achieve the final definition of the plated features. Figure 2 shows the key differences in the two processes. SAP: Key Primary Metallization Technology Considerations SAP is a production-proven process for the metallization of buildup dielectric layers with electroless copper directly on polymer resin. The advantage of eliminating copper foil fol- lowed by subtractive etch is the capability to achieve finer line/space tracks and small- er land pads required for IC Substrates. High yields can be obtained at 12/12 µm line/space with continued development going forward be- low 10/10 µm. The SAP electroless copper metallization process is similar to conventional metallization of rigid and flexible PCBs. The process has a desmear sequence, followed by surface condi- tioning and activation and finally an electroless copper seed layer between 0.7 and 1.0 µm. It is essential the seed layer of electroless copper has sufficient adhesion to the organic buildup material and to the blind microvia copper tar- get pad. This is to provide support during elec- trolytic plating of the circuitry and to withstand thermal-mechanical stresses on the features during assembly and reflow. Figure 3 shows the SAP copper-to-resin interface. A combination of chemical and mechanical adhesion is required to prepare the substrate for electroless copper adhesion. The perman- ganate desmear chemistry is used to oxidize the epoxy resin surface, providing more hydro- philicity. As the density of pin count increases, the line widths and land sizes decrease to ac- commodate the fan-out requirements. Density requirements coupled with high-sig- nal speeds mean that adhesion of the seed lay- er to the dielectric without significant rough- ening of the buildup material during desmear is a required attribute of SAP technology. This is challenging given the variety of epoxy res- ins, fillers, and glass beads or fibers available for buildup dielectrics. Commercial systems such as the Systek SAP Desmear process show compatibility with multiple commonly used substrates at below-specification roughness (Figure 3). Figure 2: SAP enables finer lines and spaces for IC substrate RDL. Figure 3: Copper adhesion at the resin-to-copper interface is a critically important metric for the semi-additive seed layer performance.