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66 PCB007 MAGAZINE I OCTOBER 2020 tors mounted on vertical spargers. The im- pingement is ideal for solution exchange in the microvias and shortens plating times while promoting uniformity. The same RDL chemis- try can be used to plate a wide variety of via diameters and depths as well as through-vias in cores without chemical adjustments. Figure 10 shows a core that was double-shot laser-drilled, metallized, and pattern plated in Systek UVF 100. Uniform height between traces of varying sizes and minimal dimple over filled vias is im- portant for ease of buildup processing. Coreless Package Substrates Many flip-chip CSP packages use a two- or three-layer embedded trace substrate (ETS) that has a coreless design. The initial layer starts as a copper carrier that is imaged on a single side with line/space down to 7/7 µm. The panel is electrolytically plated with a spe- cially formulated plating process to form very square trace corners without doming, have ex- cellent co-planarity between fine line tracks and land areas and have low internal stress to prevent warpage [1] . After plating, the resist is removed, and the panel is backfilled with resin followed by one or two RDL layers. Figure 11 shows coreless processing. Figure 12 shows a cross-sectional view of an initial M1 layer plated with Systek ETS 1200 on a VCP line. After these features are plated and the resist removed, the substrate is encapsulat- Figure 10: Double-shot laser-drilled core plated with Systek UVF 100 image before final etch. Figure 11: Coreless buildup process for IC substrate. Figure 12: Coreless substrate buildup starts with ETS plating on a removable copper carrier, which is then encased into prepreg and built up with RDL plating.