Issue link: https://iconnect007.uberflip.com/i/1299286
OCTOBER 2020 I PCB007 MAGAZINE 67 ed in prepreg to encase the traces, laser-drilled, and then the M2 layer is metallized with a 2-in- 1 plating system like the Systek UVF 100 to create the RDL. The copper carrier is stripped away, leaving extremely square traces after re- moval, providing an outer layer with fine line/ space that has superb electrical properties. Thermal Management With Through-Hole Fill Due to increases in package density, thermal management has become a key area of focus for substrate designers in recent years. Ther- mal management of interconnect platforms re- quires heat extraction from hot spots and heat transfer through the package to maintain de- sired operating temperatures. As package ar- chitecture seeks to increase the power density into smaller form factors, the total heat dissi- pation becomes more challenging. One tool available to designs is solid copper vias for IC substrate and board-level sys- tems. Through-via fill with copper is already widely used in LED lighting substrates to remove heat from the contact pads and re- duce package tempera- tures for long life reli- ability. In the example, the junction tempera- ture of the LED pack- age was lowered by 34°C with the use of copper-filled vias. There are many ad- vantages to using cop- per-filled vias com- pared to conventional plugging of the holes. The solid copper pillar- like structure is very structurally robust and will easily withstand the stresses of thermal excursions. The through-via copper has a con- sistent CTE with stacked vias to reduce thermal- mechanical stress on the substrate in assembly and life cycling. Fabrication of through copper vias has recent- ly seen an innovation using a unique single-step plating process that bridges mechanically or la- ser-drilled holes with electrolytic copper, form- ing two separate blind vias on either side, and then fills the structure to a flat surface [2] . The process is capable of filling vias with aspect ra- tios up to 3:1, cavity-free, with minimal surface copper plating. This reduces or even eliminates the need for planarization and minimizes the amount of etch to maintain tight trace geom- etries for controlled impedance. Through-vias can be formed by double-shot laser or mechanical drilling. Currently, the only available commercial process that can Figure 13: The addition of copper thermal vias significantly improves the operating LED junction temperature for longer operating life. Figure 14: Single-step through-hole filling for the core layer of IC substrates has benefits, ranging from improved thermal management to improved structural stability.