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24 DESIGN007 MAGAZINE I FEBRUARY 2021 ufacturing processes. Metal deposition pro- cesses developed for the silicon-based inter- poser enable the redistribution of the very closely spaced terminals on the die element's perimeter to a uniform and wider spaced array pattern that will enable a more efficient pack- age substrate interface (Figure 1). Although the silicon wafer packaging process has proven robust and reliable, the cost associ- ated with silicon-based interposer fabrication has been a primary detractor, and because the wafers are round, there is a great deal of sur- face area at the wafer perimeter that cannot be populated. In the effort to trim overall pack- aging expense several alternative panel-level packaging methodologies have emerged. Panel Level Packaging Both independently and through consortia of academia and industry, several viable solu- tions have evolved that provide the same fan- out and fan-in/fan-out interface capability. Panel-level packaging will continue to use sili- con as a base, but alternative lower cost organic epoxy-glass laminate and panel formatted glass are viable options. Silicon and Glass Panel Development To gain better utilization of the silicon base, some companies have moved away from the traditional wafer level format to a square sili- con or glass panel format where the individual die elements can be arranged in the same row and column format with minimal base material waste. Silicon Interposer Base Material To maximize assembly efficiency the base material can be furnished as 300 mm and 500 mm square panels, but some companies look- ing to maximize package assembly efficien- cies are fabricating panels as large as 600 mm square. Silicon-based interposer fabrication requires a rather specialized and complex sequence of processes that begin with via-hole formation. Although laser ablation can be adopted for forming the micro-via holes, the process most commonly employed for volume applications uses a deep reactive-ion etching (DRIE) pro- cess (oen referred to as the "Bosch" process). is methodology can provide very small hole diameters that range between 5–20 microns. In preparation for conductor forming and via filling, a seed layer of copper or tungsten is applied to enable electroplating the additional copper required to complete the via-fill opera- tion. Further pattern imaging and plating pro- Figure 1: Comparing the fan-out to the fan-in/fan-out wafer-level package.