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FEBRUARY 2021 I DESIGN007 MAGAZINE 25 High Tg, Low CTE Organic Base Material One of the more promising materials for the high-density organic package substrate applications is promoted as an ultra-low CTE organic glass reinforced bismaleimide triazine (BT) based laminate. While many organic dielectric materials have traditionally proven suitable for a broad range of wire-bond package applications, several leading suppliers have developed a more advanced laminate material that closely matches the very low thermal coefficient of expansion (CTE) of the silicon die element, as well as meeting the fine-line interconnect challenge for new generations of high I/O face-down mounted semiconductors. e manufacturer promises that the laminate will provide a more stable platform for mounting silicon-based semiconductor elements. e design guidelines furnished in Table 1 relate to copper alloy via filling and conductor formation for the three base material candi- dates for panel-level semiconductor packag- ing. e geometries furnished were developed from research by the author and consensus cesses are engaged to provide interconnect features on the outer surfaces of the silicon substrate. Glass Interposer Base Material Significantly less costly than silicon, glass panels are being supplied by several compa- nies specializing in manufacturing a physi- cally durable glass with properties suitable for fan-out and/or fan-in package applications. e nominal CTE of the metalized glass panel is also a ver y close match to the silicon die (3 ppm/°C). Glass is available in panel thicknesses that range from 50 μm to ≥700 μm, and the process differs significantly from silicon wafers because it will not require back grinding and polish- ing prior to via ablation and plating opera- tions. e via-hole forming processes for glass include laser and electrostatic discharge as well as mechanical drilling using micro-sand- blasting. Metallization on glass begins with a vapor deposition (PVD) process of copper or silver ink deposition to furnish the base for fill- ing vias and interconnect circuitry. Table 1: Panel-level package design guide.