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62 PCB007 MAGAZINE I MARCH 2021 Feature Article by Graham Naisbitt IPC COMMITTEE CHAIR Background e current IPC TM- SIR test is tar- geted at typical applications. at is where the minimum PCB feature is separated by more than 200 µm, and the voltage is within the approximate range of 10 to 100V. e test duration states not less than 72 hours; by com- mittee agreement this was to revert to 168 hours, but evidence is now available that flux residues may lie dormant for beyond 500 hours in service, and hence there is a need for a three- or four-week test. ere are two developing different technol- ogy regimes: 1. High voltage (~1000V) electronics for electric vehicles. 2. Low voltages and fine pitch devices (~2V and <100 µm feature size) in the medical and space industries. e existing TM- is not appropri- ate for these technologies. For example, in the high voltage testing standard ISO PAS 19295:2016(E), electric components or cir- cuits are required to operate with a maximum working voltage between 30 V a.c. (rms) and 1,000 V a.c. (rms) or between 60V d.c. and 1500V d.c An impetus for a new test has been created by the removal of the ROSE test from Rev G of JSTD-001. ere is a desire to qualify clean- ing efficacy underneath bottom-terminated components (BTC) by using a modified SIR test, along with a new test vehicle that can take advantage of low-cost test vehicles, and use SIR patterns underneath the BTC to evaluate cleaning efficacy. Following on from a current HDP User Group project into corrosion, a method will be produced to look at pitting and crevice cor- rosion through solder mask. Here, a modifica- tion of the SIR technique is proposed to eval- uate solder mask integrity and uses a new test vehicle. Aim e aim here is to develop new SIR stan- dards to cover the low and very high voltag- es, and validate the developed approach with Developing New SIR Standards

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