Issue link: https://iconnect007.uberflip.com/i/1350598
72 PCB007 MAGAZINE I MARCH 2021 TLPS pastes, which metallurgically bond to circuit pads, offer both high performance and versatility of installation that is conducive to high manufacturing volumes. Sintering pastes can be formulated with a variety of particle siz- es and flow behavior, allowing this technolo- gy to provide a spectrum solution to applica- tions from filled microvias in either a printed circuit board or semiconductor package scale, to printed bumps for interconnection of sub- assemblies, to thermal interfaces with embed- ded heat sinks. PCB constructions continue to increase in complexity resulting in ever more difficult- to-fabricate high aspect-ratio PTHs and in- creasing lamination cycles with dielectrics that do not tolerate multiple laminations well. TLPS paste-filled via layers offer an opportu- nity to circumvent many of these problems. Using TLPS paste via layers, high-aspect-ra- tio PTHs can be broken into manageable siz- es and joined in a single lamination. Likewise, for high-density interconnects (HDI), dou- ble-sided circuits can be fabricated in parallel and microvia anywhere interconnects can be made with the TLPS paste via layers—also in a single lamination. Besides eliminating low- yielding process steps and substantially reduc- ing cycle time, the use of TLPS via layers also improves high frequency circuit performance by eliminating lossy stubs. A logical extension of this long-proven PCB fabrication method is embedding discrete passive components in the same process in which the Z-axis intercon- nects are formed. TLPS pastes have been specifically engi- neered for thermal stability post-lamination. e sintering reaction of the TLPS metallur- gy, which happens concurrently with the cur- ing of the prepreg/lamination adhesive, essen- tially 'thermosets' the metallic network. e sintered vias do not remelt below 400°C but do have a fully reversible modulus drop at about 190°C to mitigate the high expansion of PCB laminates through their glass transition tem- perature. is combination of features enables the TLPS vias to withstand multiple lamina- tion and assembly cycles without degradation, as well as provide compatibility with harsh en- vironment operation. ese robust features have resulted in TLPS paste via layers' success- ful deployment as Z-axis interconnect in mil- itary and aerospace applications for over two decades. PCB007 Catherine Shearer is head of Conductive Paste R&D at Ormet. Catherine Shearer TLPS pastes, which metallur- gically bond to circuit pads, offer both high performance and versatility of installation that is conducive to high manufacturing volumes.