Issue link: https://iconnect007.uberflip.com/i/1359517
APRIL 2021 I DESIGN007 MAGAZINE 15 exploit all avenues. e idea is to lower the AC impedance of the planes. Shaughnessy: Barry, what's the cutoff ? How should a company know when it's time to either invest in a simulation tool or just start farming out simulation? Do they look at it by the speed or the rise and fall rates, edge rates, or if it's serial links? Who would you recom- mend? Olney: When it's too close for comfort, basi- cally it's time to do signal integrity analysis. ere's two ways of looking at it. ere's the old, lumped-element method working in the time domain. at's static timing or the rela- tionship between clock, data, address, and command signals. But what you must appre- ciate is that that static timing rides on an electromagnetic carrier weight. You have your static timing, which is critical, that rides on this wave of electromagnetic energy through the transmission line. We are used to visualizing the static waveforms on the oscil- loscope in the time domain, but we also need to think in the frequency domain. It's a differ- ent world working in the frequency domain compared to the time domain. e frequency domain is particularly suited to analyzing the PDN. is electromagnetic field that transports the static signals can also vary depending on whether it's running on a microstrip or a stripline configuration. If it's on the outer microstrip layer, because there's a mixture of solder mask and air in the dielectric, it tends to speed up the signal. It reduces the dielectric constant because the velocity of propagation is the speed of light divided by the square root of the dielectric constant. If you have a lower dielectric constant, then you have a faster speed. So, you must take into account the actual static timing of the devices, their rela- tionship between the clock and the data and address, plus the timing of the propagating sig- nal through the transmission lines. Shaughnessy: When you have customers come to you, what are some of the typical jobs where they should have done a simulation and they didn't? Olney: Generally, memory analysis. DDR is new territory to a lot of designers. ey want to feel confident in what they've done and make sure they haven't made a mistake. at's one reason why people get simulation done, and the other, of course, is they have a board that doesn't work, they've been trying to fix it and they need help. at's when they're desper- ate, and it shouldn't come to that; that's plan B. Simulation should be done up front, as I've mentioned before, you need to do it before you even start placing a chip on the board. Happy Holden: Are there situations where the board might work but you fail FCC? What other external things can you fail even though you connected the point, and it seems that the board works? Olney: Yes, that happens a lot with reference designs. A reference design is done by smart engineers who design chips, and they know how to do a basic PCB layout, but in general they're not highly experienced PCB designers, so they don't know a lot about design for man- ufacturability. ese new reference designs work great in the lab with a few wires hanging off here and there. Great, we've got it work- ing. ey make the reference design available, and everyone copies it thinking it's a golden board. But if you were to temperature cycle the board for the equivalent of 10 years, there are reliability issues. So that's generally what happens—intermittent problems in the field. Shaughnessy: Do you find datasheets to be helpful? Olney: I always say to assume the datasheets are wrong, especially libraries of physical compo- nents because you look at a mechanical draw-