Issue link: https://iconnect007.uberflip.com/i/1359517
52 DESIGN007 MAGAZINE I APRIL 2021 Feature Article by Bill Hargin Z-ZERO When I was cutting my teeth in high-speed PCB design some 25 years ago, speeds were slow, layer counts were low, dielectric con- stants and loss tangents were high, design mar- gins were wide, copper roughness didn't mat- ter, and glass-weave styles didn't matter. We called dielectrics "FR-4" and their properties didn't matter much. A fast PCI bus operated at just 66 MHz. As speeds increased in the 1990s and beyond, PCB fabricators acquired soware tools for designing stackups and dialing in target imped- ances. In the process, they would acquire PCB laminate libraries, providing proposed stack- ups to their OEM customers late in the design process, including material thicknesses, cop- per thickness, dielectric constant, and trace widths—all weeks or months aer initial sig- nal-integrity simulation and analysis should have taken place. Speeds continued to increase in the 2000s; design margins continued to tighten, and OEM engineers began tracking signals in mil- livolts (mV) and picoseconds (ps). Figure 1 illustrates these trends star ting in 2000, emphasizing the trajectory of PCI Express, from PCIe 3.0 in 2010 to PCIe 6.0, which is just on the doorstep. In webinars and training events I oen pose this question: "Why do we simulate?" I ask because the answers tell me a lot about the audience, and some wise older person long ago told me and my fellow students to "always know your audience." Why We Simulate Figure 1: Interconnect speed increases in gigabits per second (Gbps) from 2000. (Artwork by yours truly.)