Issue link: https://iconnect007.uberflip.com/i/1359517
20 DESIGN007 MAGAZINE I APRIL 2021 One of the things I talked about was time. A lot of people start designs when they are not ready for layout. ey say, "We started the design, and we'll give you the main proces- sor, the memory, and the power supplies," for instance. You start with these, move things around, and change them from one side of board to the other. Spin them and rotate them and whatever to get the best placement to pre- vent the rat's nest from crossing over, then route that section. Eventually the EE finishes the schematic, and you add all the other chips. "But the processor would have been better on the other side of the board." Turn it the other way around and all the signals would not be going through the center of the board from one side to the other. So, my recommendation is to never start a board until the schematic has been finished, approved, and it's ready to go. e other thing I do when I'm analyzing a design is to look at the PDN, which is very important from a stability point of view. e key points for stability in the design are stackup impedance and the AC impedance in the PDN. Adding planar capacitance by using very closely coupled power/ground planes pairs, positioned close, in the stack, to the top and bottom ICs, has a dramatic effect on reducing the AC impedance. is is where the stackup configuration needs to be adjusted in conjunc- tion with the PDN plot. Minimizing the reflections on high-speed signals is another thing. You may have a driver, and typically the source impedance of the driver is between about 10–30 ohms. But, you need to have a transmission line of say 50–60 ohms. Now, that won't match to a driver of 10–30 ohms. In high-speed design you need to have either a series ter- minator or a parallel terminator at the end of a long line. Parallel terminations simple match the transmission line impedance of 50Ω. But a series termination must be cal- culated. e iCD Termination Planner, for instance, extracts the attributes required to determine the source impedance of the driver from an IBIS models IV curves. en the series termination resistance is calculated, based on a distributed system and load, to match the transmission line for the selected layer in the stackup. In a typical digital design, you've only got the rise time to worry about, but with DDR you've got the data being clocked from both the rising and falling edges of the sig- nal. So, you need to also look at the falling edge of the waveform, and that's quite a lot faster than the rising time of the device. is is due to the design of typical CMOS output drivers. For the same feature size transistor, an n transistor can turn on faster than a p transistor. So, the fall time is always faster than the rise time—which you need to consider. Simple things like that will get your reflec- tions under control. Now, reflections create a lot of crosstalk because if you have close cou- pling on the signals, which you normally do with tightly routed boards, you don't have a lot of room. You've got to route things close, and so you get coupling and crosstalk, which creates radiation. EMI is created from all these reflec- tions. It's stabilizing the impedance and the power supply that stops these reflections and radiation allowing the product to pass EMC tests. All critical signals should be simulated. I don't actually simulate every signal within a bus. If you've got a huge bus with 128 bits, you're not going to simulate each one, but one A materials planner tool allows the user to compare Df and Dk of various materials.