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26 PCB007 MAGAZINE I JUNE 2021 Indeed, reaching fine line technology below ~2/2 mil L/S is a nontrivial task, since reliable and robust etching of un- der-2-mil lines requires well controlled copper thickness and small variations within a board as well as lot-to-lot. High-volume PCB manufac- turers, specifically those in the Far East, have the production volume and technological need to go as low as even 5-µm lines, and choose to transfer their process into PVD-based (phys- ical vapor deposition) copper coating. In this process, which is known as semi-additive pro- cessing (SAP), copper thickness is well con- trolled in a process borrowed from the semi- conductor industry. Aer etching of the thin PVD-coated copper, the final copper thickness can be reached by electroplating. is method, although reliable, involves sig- nificant investments that may not be justifiable for low-volume or specialty manufacturers like PCB Technologies. For those companies, the demand for sub-1-mil technology is not that pressing. To reach the 1-mil line/space ball- park, subtractive approaches are adequate, al- though they pose several limitations: 1. Keeping copper thickness to the lowest values possible. Copper thickness above ~20 µm will not enable subtractive processing. Average thickness between lots should be maintained to variations below 1 µm. 2. Keeping copper thickness variation to values below about ±1 µm across the board. 3. Applying appropriate thin resists for line etching, resist thickness, etc., should match the required etched thickness. e resist should be thick enough to protect the desired lines, yet thin enough to enable stable lithography and prevent high aspect ratio during etching. To support these requirements, special at- tention should be given to copper plating stages. Lowering variation at these processes may require thinking about agitation, throw- ing power, and anode shapes as well as usage of current thieves. In addition, one should be aware of copper etching processes along the process flow. Any copper etching process will adversely affect the total variation and will result in poor L/S definition. PCB007 Eran Lipp is head of R&D and Yaad Eliya is CTO at PCB Technologies. How can PCB fabricators achieve finer lines and spaces using current moderately-priced substrates? A Q

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