Issue link: https://iconnect007.uberflip.com/i/1383248
JUNE 2021 I PCB007 MAGAZINE 55 the plated and paste options, which attests to the good thermal dissipation and low electri- cal resistivity of each of these nets. Conclusion e market for high-layer-count PCBs has tra- ditionally been highly specialized to address the needs of high-end computing, military, telecom, and semiconductor test applications. Using con- ventional drill and plate process steps to build these PCBs is becoming unsupportable and has driven adoption of TLPS paste vias to overcome issues in high-aspect-ratio and high-density, leading-edge designs for over two decades. Cre- ating PCBs from several subassemblies that can be independently fabricated and joined using sintering pastes is an attractive alternative man- ufacturing strategy that leverages existing man- ufacturing flow. Both the technical performance and the cost benefit of this approach have been favorably evaluated by independent sources. As the trend to higher PCB complexity chal- lenges the use of conventional fabrication strat- egies in a greater array of applications, the de- sign versatility and process flow flexibility of re- placing one or more layers of conventional Z-ax- is interconnect with TLPS paste becomes more compelling in mass market applications. Cou- pled with now-established manufacturing flows and a solid track record of reliable performance, soware patches under development for com- mon design tools will enable wider adoption of TLPS paste interconnect as the benefit can be readily determined at the design phase. PCB007 is article/paper was presented at IPC APEX EXPO 2021 and was published in the Proceedings. References 1. U.S. Patent No: 8,840,700 2. R. E. Taylor, H. Groot, and J. Ferrier, TPRL Report 1584, "Thermophysical Properties of Conductive Ink." 3. Das, Rabindra, Egitto, Frank, Lauffer, Joh, Antesberger, Tim and Markovich, Voya, "Z-Axis Interconnections for Next Generation Packaging," Advancing Microelectronics, Vol. 38 No. 6, pp 12-19. 4. Carver, Chase; Seatrand, Norman; Welte, Rob- ert; "PWB Z Interconnect Technology—Electrical Performance," IMAPS Proceedings, Oct 2014, San Diego, CA ISBN: 979-0-9909028-0-5 5. Lauffer, John; Knadle, Kevin; "Z-Interconnect Technology—a Reliable, Cost Efficient Solution for High Density, High Performance Electronic Packag- ing," IMAPS Proceedings, Oct 2014, San Diego, CA ISBN: 979-0-9909028-0-5 6. Coupon design is the property of Insulectro, Inc, Lake Forest, CA, 92630. Coupon build per- formed by Gorilla Circuits, Inc. General design fea- tures and results shared with permission. Catherine Shearer is head of conductive paste R&D, EMD Electronics. Gary Legerton is an applications engineer at EMD Electronics.