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62 PCB007 MAGAZINE I SEPTEMBER 2022 saved manufacturing time at both the PCB fabrica- tion and assembly levels. Today the industry is facing a similar challenge with microvia reliability especially after reflow of the PCB at assembly, during rework, or operating in the field. As with the shortcomings of electrical testing in the past, the industry designed PCBs with micro- vias without evaluating the thermal properties of the material or the geometries in the design. Fabrica- tors produced the finished goods and evaluated the finished PCB to established performance standards such as IPC-6012. When difficult-to-detect failures occurred post assembly, a test method IPC-TM-650 2.6.27 was established and a caution was added to the IPC- 6012 rev E in section 3.6, Structural Integrity. The testing of a D coupon via IPC-TM-650 2.6.27 did validate that the finished PCBs were safe for assembly, but it did not stop a fabricator from building a bad design. Until now, there was not a method to simulate a PCB design that validated that the material selection, dielectric thickness, micro- via size, and configuration (single, stacked, or stag- gered microvias) could survive 6X reflows. As with the evolution of electrical test and the use of the software to validate the design and the final test, we now have software that will validate the struc- tural integrity of a microvia in a design during PCB stackup, before a design has been approved and placed into the fabrication process. This new soft- ware provides the industry a way to validate the design, fabricate a microvia design with confidence, and validate that the PCB has met the structural requirements by testing to IPC-TM-650 2.6.27. This paper will demonstrate real cases where valida- tion software has identified structural issues with a microvia design and how this software can provide modification of the PCB design geometries that will result in a working stackup. Microvia Failure Location: In the Target Pad and Plated Microvia Interface There have been many studies regarding micro- via failures. In this document, the focus is not on the location of the failure but instead elaborating on the mechanics that initiate microvia failures. The goal is to show how our industry can now plan and prevent microvia failures in a finished PCB by planning and validating a stackup at the layup stage and then sim- ulating how that PCB can survive 6X reflow cycles when the fabrication process has been completed. To date, many different studies have identified that microvias are weakest at the electroless copper interface. Electroless is deposited over the micro- via and lies between the target pad and the elec- troplated microvia. In most cases, the failed micro- via is found in the electroless at the bottom of the single microvia and almost always at the bottom of stacked microvias. Improvements in electroless copper have been made and they have improved microvia reliability. The new advanced electroless chemistry can dem- onstrate that epitaxy and bottom-up recrystalliza- tion can occur between the target pad and the elec- troplated microvia. Studies have shown that direct metallization, which does not use electroless, also achieves epitaxy and bottom-up recrystallization. In both cases, reflow testing demonstrates improved microvia reliability, but these structures can still fail and not meet 6X reflows with resistance changes less than 5%. The question arises as to why microvias are weak. They are not but simply put, microvias are butt joints and, as such, are inherently weak. Buried or epoxy filled vias require wrap plating for these types of interconnections per IPC-6012 Table 3-4 and 3-6. It is not possible to have wrap plating at the microvia tar- get pad, and the best that can be done is to improve the interface with epitaxy and bottom-up recrystal- lization. However, it should be noted that even with these improvements and with direct metallization that has no electroless, we can still create microvia failures during reflow and D coupon testing. What Causes the Microvia to Fail? During reflow there is temperature cycle material expansion of the laminate that creates stress on the microvia butt joint. When the stress created by the expansion exceeds the strain limit of the target pad and electroplated microvia interface, plastic defor- mation occurs, and non-conformance exists. Many studies have tested microvias before reflow and after reflow and have concluded that microvias This method saved product cycle time, prevented the loss of material, and saved manufacturing time at both the PCB fabrication and assembly levels.