Issue link: https://iconnect007.uberflip.com/i/1488725
62 PCB007 MAGAZINE I DECEMBER 2022 not have the necessary certification for the duty it must perform. However, all is not lost. e design can be recovered. Currently, there are two main options available to reverse engineer or recover the PCB: netlist extraction and destructive scanning. Both options pro- vide solutions to recovering the PCB. Netlist extraction: If all phototools and design data are lost but a bare PCB remains, this is a lower-cost recovery option. A "golden" PCB is preferred but not necessary. If the bare PCB has a known fault, it can be dealt with post-pro- cess. In this process, the bare PCB is scanned utilizing a high-resolution flatbed scanner. is provides the "footprint" of the PCB. e two sides are then combined using CAM so- ware and a "dumb" netlist as output. is file is taken to a flying probe with self-learn capa- bility. e bare PCB is put on the machine and the machine is instructed to learn the electri- cal intelligence of the PCB. When this is com- plete, the information is then taken back to the CAM system where an IPC netlist or neutral net can be created. is can be sent back to the customer or design bureau to recreate the pho- totools to remanufacture the PCB. Destructive scanning. Here we are using the principles of the first option to create the pho- totools for the customer. Just as in the first example, we are scanning the outer surfaces of the PCB; once the outer layers are completed, we will use precision sanding and/or milling equipment to either mill or sand the PCB to expose the next layer. is layer will then be scanned. e process will continue until all layers have been captured. Each layer is scru- tinized and carefully re-created electronically. Edits may include increasing trace widths to industry/customer requirements, fixing angles and terminations, or guaranteeing connec- tions from the scanned images. Comparing the netlist created by the self-learn to the netlist created by the destructive scanning process is an important step to remember. is can iden- tify a discrepancy between the scanning and the raw self-learn. If there are issues, design engineering can be consulted to identify the proper signature. Once this is complete, the layers can be electronically combined, and the IPC or neutral net created. In addition, the phototools, drill file(s), and other manufac- turing-related files are created. is final pack- age can then be sent back to the manufacturer/ customer for remanufacturing. All is not lost just because a manufacturer has obsoleted a legacy design. With some time, patience, and the right partner, the design can be recovered and that forgotten (but reliable) infrastructure can continue plugging along. No design is lost forever. Happy holidays to all of you and your fami- lies. PCB007 Todd Kolmodin is VP of quality for Gardien Services USA and an expert in electrical test and reliability issues. To read past columns, click here.