Issue link: https://iconnect007.uberflip.com/i/1489778
58 DESIGN007 MAGAZINE I JANUARY 2023 improve legacy tool support in 3D integration. Design portioning between chiplets, includ- ing die-to-die (D2D) connections and manag- ing thermal and off-package I/Os, are complex challenges. High interconnect densities are driving the transition from laminate design to silicon interposer design, making formal signoff of design rule check (DRC) and layout vs. schematic (LVS) a new requirement for package designers. Chiplet-based systems require that the inter- poser and the package be designed correctly. Interposers have high-speed signals, clocks, address lanes, and data buses, which require signal and power-integrity analysis. When they are tightly packed systems, power and ground impedances impact the signal reflec- tions, crosstalk, and simultaneous switching noise. is makes critical our integrated analy- sis technology, with design technology. e industry is facing many significant chal- lenges: technology acceleration, pandemics changing work patterns, and climate issues. However, there has never been a better time to work in the electronics industry, especially now that every segment is fusing in a meta- verse. Cadence aims to strengthen its partners with more vibrant design and analysis solu- tions to enhance productivity and disperse creativity. We are aggressively developing new 3D-IC capabilities, molecular modeling, RF and mmWave, automotive and aero defense solutions, multiphysics analysis from IP to chip to package to board to innovative elec- tromechanical products, and now even data centers. You can expect that AI and ML will be very much at the forefront. DESIGN007 Ashutosh Mauskar is vice president of product management and business development, custom IC, PCB and MSA products at Cadence Design Systems. Figure 3: 3D-IC Interposer and chiplets.