Issue link: https://iconnect007.uberflip.com/i/1505220
32 DESIGN007 MAGAZINE I AUGUST 2023 Our Sigrity PowerTree utility helps design- ers quickly and easily visualize their power connectivity from the schematic. It also allows them to run a quick simulation that will uncover any unnatural resistance drops or bad connections early in the design so correc- tions can be made in the schematic before they become a major problem later in the layout. Power Workflow: Layout Analysis In layout analysis workflows, engineers can collaborate with the layout designer on the board file using the previously created Pow- erTree file to analyze the DC and discover any current bottlenecks. When analyzing DC, it is important to understand the amount of VRM source current going to the IC destination, how much current the IC is drawing, and which VRMs are connected to which ICs. Because this information has already been captured in the PowerTree file, everything needed to run DC drop analysis is available in the layout environment, enabling IR drop, current, cur- rent density, via currents, etc., to be visualized (Figure 4). A thermal impact can also be performed with the electrothermal co-simulation ability in the Celsius ermal Solver to understand how high the current density is, how much heat is being generated, and if it is being dis- sipated appropriately. e AC analysis is performed in a similar manner. e designer has the board and Pow- erTree files and can quickly run an AC analy- sis to see if the hundreds/thousands of decou- pling caps are placed effectively and if the via breakouts from the capacitors are acceptable (Figure 5). e inductance for every capacitor on the selected via is shown, and the designer can quickly see any outliers in loop inductance Figure 5: PCB layout and PowerTree combine to enable analysis of decoupling cap placement. Figure 4: PCB layout and PowerTree combine to enable voltage drop analysis.