Issue link: https://iconnect007.uberflip.com/i/1505220
34 DESIGN007 MAGAZINE I AUGUST 2023 to find poor decoupling placement. If there is a small decoupling capacitor that has unnatu- rally high inductance, the implication is that something is wrong with the layout and the designer will need to change the layout before moving on. e key takeaway is that IDA can be utilized with information already obtained from Pow- erTree in the pre-layout phase, thus enabling the designer to quickly get information about the quality of the layout and act on any prob- lems early in the design process. SerDes Compliance Design Flow A SerDes transceiver operates at extremely high frequencies, which presents many issues and leaves very little room for design errors. A SerDes design, without equalization, may not have an open eye at the receiver, so equaliza- tion at the TX and RX is simulated with IBIS- AMI models to show the eye opening. At high speeds, layer transitions are sensitive, the cor- rect dielectric material must be selected, and even via placements become important to minimize channel impact. e PCB designer designing high-speed SerDes channels typically works with an SI expert in the early phase of the design on the via structure. An optimized via structure can make the difference between passing and fail- ing a serial link compliance test. SerDes Design Challenges/Solutions e basic rule of electrical engineering is that the higher the speed, the more details must be considered. Smaller structures that could pre- viously be ignored in lower-speed designs can have a catastrophic effect at high speeds if not designed properly. Vias can cause impedance discontinuities and negatively impact signal quality. erefore, via structures need to be carefully designed so that their behavior is pre- dictable. is is traditionally addressed during the schematic phase by pre-designing each via within the structure to work at the speed of the design. is time-intensive manual pro- cess can be made more efficient with technol- ogy embedded in the design tool to design, simulate, and optimize vias for high-speed signaling. Sigrity Aurora workflows include a via wizard, which quickly generates Allegro- based via structures. With this automated flow, engineers can create their own via structures in the very familiar Allegro environment and Figure 6: The Sigrity Aurora via wizard workflow efficiently generates Allegro-based via structures to be analyzed and optimized with Clarity 3D Solver.