Issue link: https://iconnect007.uberflip.com/i/1511130
54 DESIGN007 MAGAZINE I NOVEMBER 2023 Designing a memory interface is all about timing closure. Each signal's timing needs to be compared to the related clock or strobe signal in such a way that the data can be captured on both the rising and falling edge of the strobe— hence the term double data rate (DDR). e increase of data rates to 7800 MT/s for DDR5 has made the timing margin associated with each rising and falling edge even tighter. Table 1 lists the various timing delays of a DDR3 memory interface running at 533 MHz. Aer allowing for the chip-level delay, setup and hold times, slew rate derating, clock skew, and jitter we are le with a total margin of just 41 ps on the setup time. Even at this relatively low clock frequency of 533 MHz, 10 ps is all the margin we have le for the board-level delay. Increase the crosstalk or jitter and we are look- ing at imminent system failure. So, the velocity of propagation of the electromagnetic wave of energy through the PCB is now very signifi- cant. Most systems, whether at the chip or board level, operate synchronously; as such, voltage levels must rise or fall within a specified time or else the circuit will be out of sync and fail- ures will occur. e timing budget tells us how much margin we have, or to put it another way, how much headroom we have before a failure occurs. So, how do we go from a timing spec (Figure 1) to the actual flight time of the entire mem- ory interface? e signal and timing, relative to other sig- nals, ride on an electromagnetic carrier wave at various speeds, depending on the surround- ing dielectric materials. is energy transports the signal from the driver along the transmis- sion line to the load and does not disrupt the original timing but rather adds the same delay to all the signals that travel the same path. So, one must keep all the relative signals on the same path (layer) or there will be discrepan- cies when the signals arrive at the load. Alter-