Issue link: https://iconnect007.uberflip.com/i/1511625
40 PCB007 MAGAZINE I NOVEMBER 2023 ity of a process, procedure, machine, or mate- rials. ere are numerous features on each coupon such that they can be tailored to cap- ture current capability. Complex as these are, they cannot be inspected or sorted, so they truly represent what is going on. For novice users, the temptation is to inspect them to get perfect samples. is usually proves to be a futile activity, as some features are, by design, beyond our current capability. ese coupons are all customizable by CAT: • Conductor spacing (1 to 20 mils), via diameter, via land, daisy-chain sequence, number of layers, registration sensitivity and layers, via structure (through, blind, buried, skip vias, stacked, sequentially laminated, etc.) • Impedance type (single-ended, differen- tial, edge-coupled, broadside, coplanar, etc.) • Overall thickness, as well as placement and panel size Some coupons were designed to be removed and put in small testers 5 . e primary equipment is shown in Figure 4g. is was designed by Sandia and consists of an alignment system, fixtures, and a bed- of-nails connected to a sensitive AC-chopped, 4-wire Kelvin resistance measurement system (Figure 4j) feeding a PC. In 1999, a portable system was designed so that readings could be made in production, using an Agilent 34401A voltmeter (Figures 4h and 4i). e portable system has additional coupons from 0.33" x 3.0" to 0.5" x 2.0" to facilitate placing on pro- duction panels, as well as soware to auto- matically calculate responses. To improve the impedance measurements, the Polar RITS-510 robotic probe and measuring unit were added in 2003. IPC-PCQR 2 Benchmarking Panels Figure 4k shows a 14-layer via rigid PCQR 2 board illustrated by cross-section showing thickness ranges and various through-holes, blind, buried, subcomposite, and back drilled vias. In Figure 4l, various layers, panels, and structures are available under the IPC PCQR 2 program. HATS and HATS 2 TM Highly accelerated thermal shock (HATS) was developed in 2003 and HATS² technol- ogy was released in 2020 to add the capability to perform multiple cycle convection reflow sim- ulation up to 260°C in accordance with IPC- TM-650 Method 2.6.27B, Method 2.6.7.2c, and other custom reflow profiles. is convec- tion reflow simulation methodology with high speed in-situ resistance measurements can detect cracks and separations in the via struc- tures that occur during the high heat/expan- sion of convection reflow which could recon- nect mechanically at lower temperatures and not be detectable. HATS can test up to 72 of the IPC-2221B Type D coupons (Figure 5a-g) and 36 traditional HATS or single via HATS 2 cou- pons for both multiple cycle convection oven reflow simulation and thermal shock/cycling between 55°C and 260°C (Figures 5c–g). e seven nets in a HATS 2 are: • Net 1: 36 via daisy chain of layer 1 and 2 microvia structures only (entire via struc- ture is built on coupon but only microvia structure is measured) • Nets 2 and 3: Single vias of layer 1 and 2 microvia structures only (entire via struc- ture is built on coupon but only microvia structure is measured) • Net 4: Entire via structure through the entire PCB including buried via is measured. • Nets 5 and 6: Single vias of layer n/n-1 microvia structures only (entire via structure is built on coupon but only microvia structure is measured) • Net 7: 36 via daisy chain of layer n/n-1 microvia structures only (entire via structure is built on coupon but only microvia structure is measured)