Issue link: https://iconnect007.uberflip.com/i/1511625
42 PCB007 MAGAZINE I NOVEMBER 2023 A typical coupon is seen in Figure 6a. is is one that the OEM supplies for an IPC Class 3 board. is one has through-holes, blind microvias, and buried vias using a high-Tg, low- loss laminate. Two of these coupons are built with every board, and until an approved num- ber of IST cycles are passed, it is not assem- bled. Failure means a return to the fabricator for analysis. e IST method measures changes in resis- tance of vias and internal layer connections as the holes are subjected to thermal cycling. e thermal cycling is produced by the appli- cation of a high current through the resistive internal layer connections of a specific group of holes, usually 200 daisy-chained vias, intercon- necting through two adjacent layers called the power circuit (Figure 6c). Switching the cur- rent on for three minutes creates heat to take the connections from room temperature to a designated higher temperature. Stopping the current and with forced-air cooling, the con- nections cool in two to three minutes (Figure 6f ). Another group of interconnects, two inde- pendent daisy chains interconnecting 500 vias through any two inner layers at various levels, the ones under test, are the sense circuits (Fig- ure 6b). An isometric view of the two sets of interconnects, running parallel to and sequen- tially overlapping, is seen in Figure 6d. e equipment providing the coupon fixturing, current, cooling and resistance measurement is seen in Figure 6e. An accelerated failure will occur because of the differential thermal expansion of the inter- connect structure. Failure can occur in several locations (Figure 6g), either a via crack, post Figure 6 (left): Interconnect stress test (IST) is a DC current-induced thermal cycling test: a) Typical 6" coupon; b) Sense circuit daisy chain; c) Descrip- tion of current IST coupon; d) Isometric view of par- allel and overlapping power and sense circuits; e) IST power, data acquisition, and fixturing test equip- ment; f) Typical heating-cooling cycle; g) Failure modes of thermally stressed interconnects 6 . s