Issue link: https://iconnect007.uberflip.com/i/1526407
22 DESIGN007 MAGAZINE I SEPTEMBER 2024 materials, and choice of suitable IC pack- ages, just to name a few. ese factors are not exactly new to the industry, but with the sil- icon-to-system concept, additional focus and attention is needed. is may require more PCB designers to level up from basic board design to advanced board designs with silicon and package knowledge. People have been talking about a "conver- gence" of PCB and IC design, with each dis- cipline having a solid understanding of the other. Are we approaching this convergence in the near future? e co-design concept for IC to package to PCB is currently available from the major CAD vendors. One very viable option is for the PCB designer to move toward packaging design. Some PCB designers with IPC's CID training will have a fairly seamless transition into advanced package designing at the inter- poser or substrate level. But for a PCB designer to move into IC design is less straightforward, and vice versa. ere are similar concepts in the physical lay- out process, but it may take much longer to adapt and learn each other's environment. is would require a proper transition training program aimed at achieving this objective. ere is no definite timeline for achieving this, as it is highly dependent on the compa- nies and their strategies. How soon can prod- uct companies that embrace a silicon-to-sys- tems approach adopt this co-design platform? It could take five years or 20 years. Is there anything else you'd like to add? I would like to encourage the PCB designers to take the opportunity to level up to advanced board designs and welcome new prospects and challenges in advanced IC packaging design and IC layout design. Nothing is impossible. Find a way, stay focused, and stay interested. Thank you, Soo Lan. ank you for the opportunity, Andy. DESIGN007 the semiconductor and package knowledge gap through re-skilling or upskilling training programs. There's a lot going on at the packaging level as silicon continues to shrink, edge rates rise, and Moore's Law runs out of steam. How do you think this will affect PCB designers and design engineers? e impact is most likely seen on the IC designers at the physical layout stage. is is because the silicon (transistor) shrinkage has an immediate relationship to the physical dimensions through the mask design for the fabrication process. Moore's Law is predicted to maintain its momentum with the next generation of FET (field effect transistors) known as CFET (Com- plementary FET) until 2037, according to the 2022 IEEE International Roadmap for Devices and Systems. e current technologies in use are FinFET, GAA (Gate-All-Around) FET, and Intel's RibbonFET. e bottleneck of silicon speed has always been external to silicon, which is at Level 1 of the package. PCB designers must deal with packages placed on the Level 2 PCB. e focus on silicon to systems usually signifies an advanced elec- tronic product at Class 3 and above. PCB design- ers must look at design considerations in addi- tion to DFM, DFA, and DFT to further include DFR (design for reliability) at the advanced level to fulfil the system specifications. Examples to consider are factors like proper component placement, optimized routing, controlled impedance, thermal management, signal integrity simulation, evaluating PCB " e boleneck of silicon speed has always been external to silicon, which is at Level 1 of the package. "