Issue link: https://iconnect007.uberflip.com/i/1526407
26 DESIGN007 MAGAZINE I SEPTEMBER 2024 are now commonplace in most digi- tal designs. ese high-speed, high gate/pin count devices, which once only provided glue logic, are now offering embedded processors, digi- tal signal processors (DSPs), graph- ics processors, memory blocks, and numerous input/output (I/O) pins in one massive ball grid array (BGA) package, not to mention the consid- erable number of power supplies required to power these devices. Accommodating 30 to 40 individual power supplies to the active devices is now commonplace. is added complexity has introduced many PCB layout challenges beyond the obvious fanout and route of the fine- pitch BGA. e primary issue is generating optimal FPGA pin assignments that do not add vias and signal layers to a PCB stackup or increase the time required to integrate the FPGA with the PCB. Engineers generally do not consider FPGA pin assignments that expe- dite the PCB layout. Hundreds of logical sig- nals need to be mapped to the physical pin-out of the device and harmonized with the routing requirements while maintaining the electrical integrity of the design. To further frustrate the situation, the FPGA I/O assignment is typically in a constant state of flux throughout the design process. Con- sequently, many PCB designs must be reiter- ated simply because the board and the FPGA design teams did not have the I/O pin-out syn- chronized. is has happened to me in the past. e board may go through the process of pre- layout simulation, place, and route, and then a post-layout simulation to verify all the timing is perfect, only to find on testing the assem- bly that the FPGA I/O pin-out is incorrect on the BGA footprint. Meanwhile, aer days of delays, I re-routed, ran design rule checks, re- simulated the layout, and exported the deliv- erables. However, delays can have financial implications. Figure 2 shows the rather disorganized I/O connections of a first-pass FPGA pin assign- ment. is is typically what a PCB designer has to deal with—straight from the FPGA place-and-route tools. To make this more routable, the designer needs to adjust the pin assignment to first be on one outer edge of the BGA and then order the pins to eliminate cross-overs. Even if we manually reassign the pin-out, the problem now is how to back-annotate this modified BGA pin assignment to the FPGA design tools. e manual process is time- consuming, tedious, and error prone. e key issue is to ensure consistency between the tool sets used in the hardware description language (HDL), FPGA, and PCB environments. We must properly represent the language-based HDL representation of the FPGA as a sche- Figure 2: The dispersed connections need to be optimized to eliminate crossovers.