Issue link: https://iconnect007.uberflip.com/i/1526407
28 DESIGN007 MAGAZINE I SEPTEMBER 2024 • Accommodating 30 to 40 individual power supplies to the active devices is now com- monplace. is added complexity has introduced many PCB layout challenges beyond the obvious fanout and route of the fine-pitch BGA. • e primary issue is generating optimal FPGA pin assignments that do not add vias and signal layers to a PCB stackup, or increase the time required to integrate the FPGA with the PCB. • Many PCB designs have to be reiterated simply because the board and the FPGA design teams did not have the I/O pin-out synchronized. • To make a layout more routable, the designer needs to adjust the pin FPGA assignment. • e problem is how to back-annotate this modified BGA pin assignment to the FPGA design tools. • I/O optimization tools can provide parallel paths of FPGA and PCB design, trimming days from the design process and delivery schedules and providing significant overall long-term cost benefits. DESIGN007 Resources 1. Beyond Design: "FPGA-PCB Design Chal- lenges" by Barry Olney 2. "FPGA I/O Features Help Lower Overall PCB Costs" by Dave Brady, Siemens EDA Barry Olney is managing direc- tor of In-Circuit Design Pty Ltd (iCD), Australia, a PCB design service bureau that specializes in board-level simulation. The com- pany developed the iCD Design Integrity software, incorporating the iCD Stackup, PDN, and CPW Planner. You can download the software at www.icd.com.au. To read past columns, click here. by Hannah Grace There are many considerations when planning and designing a board layout, and factors that include signal integrity, electromagnetic interference, and power integrity must be considered. Newer board designers often forget one factor crucial to a PCB's performance and reliability, namely board parasit- ics, which usually refers to an unintended electrical effect in electronic components and interconnec- tions. This can often lead to significant changes in the physical characteristics of the layout of the PCB. Typically, in board design, parasitics look similar to the length of a trace or a wire. Each trace is slightly resistive, slightly inductive, and slightly capaci- tive. These are commonly known as parasitic capacitance, parasitic induc- tance, and parasitic resistance. The Impact of Managing Parasitics Managing parasitics in board design can have a significant impact on the physical characteristics of board performance and reliability. Typically, signal integrity, power integrity, frequency response, timing, and delay, as well as EMI/EMC considerations, rely on parasitic manage- ment for certain design traits. A simulation without parasitics can compromise the design and ulti- mately cause it not to perform as intended. The impact of parasitics on signal integrity, and parasitic elements such as capacitance and induc- tance, can lead to signal degradation, additional undesirable noise, and those potential unwanted errors in data transmission. High-frequency signals are particularly susceptible to the effects of parasitics on signal integrity. Parasitics can also influence the distribution and integrity of power through a PCB, potentially causing loss of power and instability in power- sensitive applications, as well as inef- ficient energy transference through- out the board. Continue reading... THE NEW CHAPTER The Impact of Parasitics on PCB Design