PCB007 Magazine

PCB007-Nov2024

Issue link: https://iconnect007.uberflip.com/i/1529411

Contents of this Issue

Navigation

Page 89 of 105

90 PCB007 MAGAZINE I NOVEMBER 2024 e last section applies to two or more build- up layers over a core—Type III. If fabricated sequentially, the last set of surface blind vias becomes buried vias as they are covered by the last HDI layer. A key concern during the development of these design rules was being able to capture the diversity of capabilities of fabricators and the interaction of design rules and structures that cause abnormally poor yields. As a com- mittee, we finally decided that the best way to illustrate this large variability was to clas- sify the minimum geometries into four design categories from A–D. Any known poor design practices of the design rules would be called out as a warning. Table 1 shows a sample of a design rule for a Type II HDI structure, with examples for Category D from IPC-2315 and Level C from IPC-2226A, Sectional Design Standard for High Density Interconnect (HDI) Printed Boards. Revision B for IPC-2226 will be released soon. e IPC committee working on these stan- dards had concerns that these design rules were based on the reported capabilities of fabri- cators and the needs expressed by OEM board designers. But what of yields and cost? You can claim any design rules, but can you build it? is concern may now have a solution. Ron Rhodes and Tim Estes of Conductor Analysis Technologies, Inc. (CAT) have devel- oped process characterization coupons for basic PCB fabrication processes. ey wrote 2 about these coupons and provided many reports about how this is used to characterize production, set design rules, qualify vendors, and function as responses for design of exper- iments (DOE). eir current coupons have been designed to measure the capability of HDI fabrication and can be adapted to UHDI. With this tool, I see the need to use these coupons and panels to measure the yields, interac- tions, and capabilities of HDI and UHDI pro- cesses and design rules that we have put in IPC standards. e capability of different HDI processes can then be compared to the levels A–C (Figure 1). Figure 1 starts with the bottom box—the Figure 1: Performance panels with various coupons are one way to couple manufacturing capability with acceptability and design standards. Replication and distribution of the coupons on the performance panel is important for a statistically significant result that will translate into costs and profits.

Articles in this issue

Archives of this issue

view archives of PCB007 Magazine - PCB007-Nov2024