Issue link: https://iconnect007.uberflip.com/i/1537388
50 DESIGN007 MAGAZINE I JULY 2025 C O N N ECT T H E D OTS enabling electroplating later in the process. The sub then goes through imaging again, but this time, instead of applying a full image, we only expose the through-holes. This allows us to plate copper into the holes without affecting the sur- face copper on layers 2 and 5. After the copper is plated, we remove the resist, thereby expos- ing the underlying copper. The sub then goes through epoxy via filling and copper planarization. The panel then returns to imaging to create the copper circuitry on layers 2 and 5. Next, we etch the sub-panel, strip the photoresist, and prepare it for re-lamination. This time, pre-preg is applied to both sides of the sub build, and we add copper foil to the outside surfaces to form layers 1 and 6. We then press the parts, and the panel is ready for microvia creation. For the microvias, the panel is first sent to imaging, where we apply a photoresist with an image consisting only of dots, each represent- ing the diameter of a microvia. The etching pro- cess removes these dots, which removes the copper and exposes the laminate underneath. We remove the resist, and the panels are ready for the laser process. CNC lasers are used to ablate the dielectric material down to the copper landing pad. Ablating all the dielectric material is important, but it's also important not to overdo the process. Once the las- ing process is complete, we drill through-holes in the panels. Aligning the laser-drilled microvias and these holes to the sub below is critical for making good PCBs. After creating the holes, thorough cleaning removes laser residue and activates the copper on the panels, preparing them for plating. Then, we re-process them through the electroless cop- per process. With metal now in the through-holes and microvias, the panels go through another imaging step to create the circuitry on the exter- nal layers. Once imaged, we copper electroplate the parts (covering the circuitry, through-holes, and microvias), then electroplate with tin to protect the newly added copper. We remove the photore- sist, etch away the copper below, and remove the tin. At this stage, the panels are ready for inspec- tion and solder mask application. This is one pro- cess sequence for the most basic sequentially-lam- inated structures. Some designs or requirements may alter this process sequence. Yield Detractors The added processing steps for the sequential laminated parts impact lead times and cost. Here are some potential areas where yield loss is possi- ble in the manufacturing process. • Via reliability failures » Registration, especially with stacked microvias » Insufficiently plated vias or voids in via-fill • Delamination » Inadequate bonding between layers • Registration issues » Misalignment between layers due to multiple processes. A general rule of thumb for setting expectations on lead time: Every required lamination process adds a week to the lead time. Cost Drivers Unsurprisingly, sequential lamination is one of the most expensive cost drivers in the PCB manufac- turing process. Here are cost drivers to consider when designing: