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24 DESIGN007 MAGAZINE I NOVEMBER 2025 capacitance, and multiple tightly coupled ground- power pairs. Dielectric materials in signal layers are chosen for their low loss tangent (Df) and low dielectric constant (Dk) to support high-speed sig- nal integrity. For power delivery, materials with low Df and high Dk are paired with tightly spaced power and ground planes to maximize planar capacitance and improve decoupling performance. Also, thermal management demands the integra- tion of heat spreaders directly within the PCB lay- out. Copper pours and multiple thermal vias must be precisely aligned with the GPU die and voltage regulator module (VRM) regions to facilitate effi- cient heat dissipation. The layout must also accom- modate liquid cooling interfaces, including provi- sions for cold plate mounting, mechanical keep-out zones, and accurate thermal pad placement. However, the real challenge lies in achieving micro- ohm AC impedance (<1 mΩ) across the power deliv- ery network, especially when conventional high- speed designs typically only reach several milli- ohms at best. This level of performance requires a combination of advanced techniques, including: 1. Large, solid, uninterrupted copper planes avoid splits, cutouts, or segmentation, and ensure full-layer copper coverage for the core VDD and GND. This maximizes conductivity and minimizes inductance and resistance. 2. Increase copper thickness uses 2–4 ounces of copper for power layers. Thicker copper reduces both DC and AC resistance, and is essential for high-energy paths in AI GPU boards. 3. With tight power-ground layer pairing, place power and ground planes adjacent in the stackup, use multiple planes in parallel to reduce impedance, and a high Dk dielectric with thin spacing (e.g., 3 mils) to increase pla- nar capacitance. This lowers impedance at high frequencies and improves decoupling. 4. Optimize via arrays, which uses dense stitch- ing vias between power and ground planes, employs via-in-pad, back-drilled, and filled vias to reduce inductive effects, and helps maintain low impedance across layers and improves thermal flow. 5. To minimize loop area, route high-speed signals with tight return paths over ground planes, which reduces loop inductance and EMI, and is critical for maintaining signal integrity in high-speed designs. 6. For multi-phase VRMs, divide voltage regu- lation across multiple channels. This archi- tecture improves efficiency, thermal perfor- mance, and power stability. 7. For embedded capacitance materials, such as ZBC2000, 3M ECM or FaradFlex, offer built-in decoupling above 1 GHz. This enhances high- frequency noise suppression without discrete capacitors and supports micro-ohm impedance targets in dense multilayer PCBs. The NVIDIA H100 GPU has substantial high-den- sity on-die capacitance with low impedance path- ways, but it is not sufficient on its own to meet the ultra-low impedance demands of the power delivery network, especially under high-frequency switching conditions. Achieving micro-ohm AC impedance, well below the milli-ohm threshold, requires metic- ulous optimization across the entire power delivery network, including copper geometry, layer stackup, via architecture, low ESL decaps and embedded planar capacitance. The key to achieving ultra-low impedance lies in implementing multiple parallel power-ground planes and maximizing planar capacitance through tightly spaced power-ground pairs. An additional plane pair in parallel reduces the overall impedance by half and doubles the capacitance available for high-frequency decoupling. Above 1 GHz, this approach becomes critical, as discrete decoupling capacitors introduce lead and loop inductance, limiting their effectiveness in reducing impedance. Such high-frequency per- formance is vital for AI-driven GPUs, which require exceptionally low impedance to maintain stability and efficiency under demanding workloads. Key Points • The AC impedance of the AI-driven GPU systems must be maintained in the micro-ohm range. • They necessitate multiplane stackups with heavy, wide power planes and densely packed via arrays. B E YO N D D ES I G N