Issue link: https://iconnect007.uberflip.com/i/1541169
NOVEMBER 2025 I DESIGN007 MAGAZINE 13 It is important to note that more complex interac- tions are at work here than just the plane's capac- itance. Modal resonances, spreading inductance, and other factors also play a part, and the field solver accurately captures them. Experiment 4: Decreasing Spacing Between Planes In this experiment, we will decrease the spacing between the planes to 1 mil, which is quite small. Additionally, the dielectric constants are set back to their original values of 4.3, and the board is made large (64 in 2 ). The capacitance of this setup is cal- culated as 6.39 nF. The peak noise voltage is 31.2 mV (Figure 6). Notice that the noise voltage is sub- stantially improved over the previous cases, and even more so than the high dielectric case. Setting the board size back to 16 in 2 results in a peak noise voltage of 32.8mV. The additional capacitance formed by increasing the board by four times the original size has made almost no difference in the total noise voltage because it is out- side of the calculated effective area. Experiment 5: Increasing the Number of Power Planes In the previous experiments, we focused on what could be done when using a single power plane pair as the main source of PCB capacitance. What if we were to use two separate plane pair structures, both at a physical size that is similar to the size of the effective decoupling radius? The stackup is altered so that Layers 6 and 7 are also connected to VCC1_5. The dielectric constant is set back to 4.3, and the spacing between plane pairs is set to 3 mils. Figure 7 shows the simulation's results, with a peak noise voltage of only 39.1 mV at the cur- rent sink. Further reducing the plane spacing to 1 mil results in a peak noise voltage of only 15.4 mV. You may ask when a scenario like this is appropriate. Consider a memory system such as DDR4. Often, the manufacturer will specify that byte lanes be routed on different layers for crosstalk, timing, and other constraints. In a system like this, you will likely be forced to use multiple split planes for your PDN to accom- modate other devices. For a system like DDR4, it makes sense for all signals to use F i g u re 6 : T h e re s u l t s of t h e s i m u l at i o n fo r E x p e r i m e nt 4. T h e d i e l e ct r i c c o n st a nt i s 4.3 , w i t h t h e s p a c i n g b et we e n L aye rs 2 a n d 3 e q u a l to 1 m i l . T h e p e a k n o i s e vo l t a g e i s fo u n d to b e 31 . 2 m V, s u b st a nt i a l l y i m p rove d ove r t h e 87.1 m V fo u n d i n E x p e r i m e nt 2 . ▼ F i g u re 7: T h e re s u l t s of E x p e r i m e nt 5. L aye r 6 i s n ow c o n n e cte d to L aye r 2 by st i tc h i n g v i a s to i n c re a s e t h e ef fe ct i ve c a p a c i t a n c e c o n n e cte d to t h e c u r re nt s i n k . B ot h L aye rs 2 a n d 6 a re s i ze d s o t h at t h ey a re s i m i l a r to t h e c a l c u l ate d ef fe ct i ve a re a . T h e p e a k n o i s e vo l t a g e i s o n l y 3 9.1 m V. ▼ Kirk Fabbri