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112 I-CONNECT007 MAGAZINE I APRIL 2026 the fab of the board and substrate), it is easy for things to get lost in translation. I have watched designs handed to the fabricator with significant flaws, whether they concern mate- rial selection and signal integrity, lines and spaces too fine for the fabricator to succeed, or stacked microvias without understanding the potential for microvia interfacial fracture (MVIA). If there were no set rules, the process would be a free-for-all. Designers often break these rules in the name of efficiency and optimum electrical per- formance. This often leads to product failure and multiple and costly respins. That's why design rules (and understanding each party's constraints) are parameters that, when fol- lowed, will ensure an accurate design. It requires checking the design process step by step with all parties involved: fabricators, assembly, and the sili- con fab for the interposer. It includes electrical rule checks (ERC) for the schematic and design rule checks (DRC) for the PCB and substrate. These rules serve a specific purpose. Think of them as gates that one must pass prior to moving to the next step. For example, the designer works with data to create a schematic. Once that is complet- ed, ERC checks are required to validate whether the design is electrically correct. The ERC needs to give a clean report. If there is anything off, stop and fix the issue right away, as they can't be fixed later in the process. When designers were pushing the software to deliver the most efficient design, was there a discussion with the board and substrate fabricators about whether the design could be manufactured reliably? Perhaps the OEM has communicated in the Statement of Work that the entire package (Z- axis) can only be so high, including the substrate thickness, the height of the chip or chips on the interposer, the interposer-to-substrate distance, the protective lid for the package, and the thick- ness added by the solder. Imagine if the design- ers completed the tedious task of routing signals, designing the stackup, providing the drill file, etc., only to learn that the substrate as designed is too thick to fit in the socket on the product board. This is precisely why the designer must be cog- nizant of the constraints up front before going too deep into the design process. The fabricator and assembly firm should be involved from the outset. A Few Caveats If the rules are not set or are set incorrectly, you should understand how the board/substrate pack- age will be used. Is this a package for AI, or an ultra HDI design for very high-frequency applica- tions? Is it needed for high-power? The design rules will differ depending on what the circuit is supposed to do. It's important that issues arising early in the de- sign phase not be ignored. Signal integrity mod- els, for example, can predict signal loss at various frequencies. What if the modeling shows issues with overshoot and undershoot? Address it imme- diately, not when the design is transferred to the fabricator for manufacturing. Finally, check the design rules at each step and follow them throughout the design process. This will save heartache later. Finally, don't underestimate the need for con- stant communication and collaboration with all par- ties involved, including the OEM, the EMS provider, PCB fabricator, and the substrate and chips/inter- poser teams. I cannot stress the need for transpar- ency enough, and for the parties involved in the fabrication process to communicate their manu- facturing capabilities and constraints to the design team. There are no trade-offs here. I-CONNECT007 Michael Carano brings over 40 years of electron- ics industry experience with spe- cial expertise in manufacturing, performance chemicals, met- als, semiconductors, medical devices, and advanced pack- aging. To read past columns, click here. " That's why design rules (and understanding each party's constraints) are parameters that, when followed, will ensure an accurate design."