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58 I-CONNECT007 MAGAZINE I APRIL 2026 one quarter-size of what they had been before. Of course, it was to scale things down and make the board much smaller. Placing and soldering the SMT components directly onto the PCB's surface was perfect for automation, which had become much more widely used in assembly. When the in- dustry moved over to SMT, it had everything to do with the silicon driving the ability to fit more dies on a wafer. Again, we are seeing silicon driving PCB technology in a different direction with HDI and UHDI, and now, package substrates. Your tutorial this week is called "PCB Design Engineer's Introduction to High Density Semicon- ductor Packaging Technologies." I've also noticed that your column has shifted away from standard PCB design challenges. What will you cover in the tutorial, and what do you hope that designers will take away? I begin with a simple review of legacy components, showing where surface mount and miniaturiza- tion started and eventually evolving to variations of ball grid array (BGA) semiconductor packaging. As we have experienced over the past couple of decades, we have continued to see semiconduc- tor companies add more functionality to the die elements, increasing bond pads or bumps per die, and consequently, the packages for those die ele- ments follow suit, getting smaller and their termi- nals increasingly closer together, a challenge for both PCB designers and manufacturers. Manufacturing methods had to change to keep up with the semiconductor package technology that was being implemented. Here we are again, seeing the next evolution of this process to accom- modate a whole host of new components with a terminal pitch not even considered possible five years ago. It's a matter of scale. To support the industry's goal of onshoring key technical skills, we need to learn to design and fabricate very high-density package substrates and interposers, beyond just PCBs. The interposer will furnish a great deal of interconnect between these fine- pitch semiconductor die elements mounted on its surface. The power, ground, and in/out interface is then routed through plated via holes and spread out to a wider spaced array terminal pattern on the opposite surface. The wider pitch terminal pattern will better accommodate termination to the next level package substrate or circuit board. The traditional monolithic, system-on-chip (SoC) fabrication put all the functions into one single piece of silicon. With the introduction of multicore processor development, the semiconductor core(s) and their related support functions were integrated onto a single silicon base; the semiconductor die outline became excessively large, difficult to pro- cess, and yields became unacceptable. To improve process efficiency and overall manufacturing yield, developers of the newer generation, multi- core processors opted to separate the supporting functions—memory, I/O, specialized accelerators, digital signal processors, as examples. These now singulated functions have been classified as chiplets, configured to mount onto the interposer in proximity with the core processor's die. We used to call these configurations multichip modules (MCMs). Chiplets are just another evolution step in semiconductor package technology we now refer to as heterogeneous packaging. So, for the PCB design engineer developing the interposer or package substrate, the software tools are available; it's really just a matter of scaling and applying the design rules for chiplet land patterns and what is classified as ultra high density (UHDI) circuit routing strategies. The bottom line is that a significant amount of time and resources are invested in developing and fabricating these high- performance processors. Using what the industry is referring to as the "LEGO" approach for system- " To support the industry's goal of onshoring key technical skills, we need to learn to design and fabricate very high-density package substrates and interposers, beyond just PCBs."