Issue link: https://iconnect007.uberflip.com/i/1546933
OCTOBER 2026 I SMT007 MAGAZINE 57 surface brightness masking took less than 10 minutes. In other words, post-processing of the unpainted BGAs took less than 5% of the time needed for painted BGAs. Processing all acquisi- tions within a thermal profile can be done in a frac- tion of the time it would otherwise take. Application Specific Approach The removal of solder balls for BGA thermal warpage testing remains the industry standard, and no general recommendation is made here to replace this method for all sample types. A sample-specific threshold is needed to deter- mine when these newly presented approaches are appropriate. Larger, thicker samples are expected to show greater mismatch between top and bottom shapes and have few issues with ball removal, making the standard approach effec- tive. The samples in this study were selected for their package body thickness (0.50–0.85 mm) and serve as practical examples for the alterna- tive method presented here. Thus, samples with less than 0.85 mm thickness are suggested as a starting point for these alternative methods, requiring additional industry feedback needed to refine guidelines. Additionally, a minimum solder ball size could serve as a rule for cases where effective ball removal becomes impractical. Conclusion Measuring unpainted BGAs with solder balls still intact offers a valid alternative to current methods, preserving sample integrity and avoiding surface damage that can occur with physical shearing of solder balls. As components continue to decrease in size, shearing may become impractical. Elimi- nating painting and extensive post-processing significantly reduces time, making surface bright- ness processing of unpainted BGAs an efficient alternative to analyzing painted ones. Further time savings can be achieved by eliminating both sample painting and post-processing of solder balls by focusing on measuring the top surface. SMT007 At Akrometrix, Neil Hubble is president, and Chris Gastaldo is a senior application engineer. References 1. "Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature," JESD22- B112C, JEDEC Solid State Technology Association, November 2023. 2. "Measurement Methods of Package Warpage at Elevated Temperature and the Maximum Permissible Warpage," JEITA ED-7306, Japan Electronics and Information Technology Association, March 2007. 3. "Reflow Flatness Requirements for Ball Grid Array Packages," SPP-024 Issue A, JEDEC Solid State Technology Association, March 2009. Sponsored link: akrometrix.com Neil Hubble Chris Gastaldo