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22 The PCB Magazine • April 2014 lectively accerlates the deposition of the copper from the bottom, up, while the carrier and lev- eler componets of the addition agent package work to minimize overplating on the surface. Certainly, other parameters play a role in this as well. Generally, higher copper/lower acid ratios of the electrolyte benefit bottom-up filling, as does direct impingement solution movement as opposed to air agitiation. Secondly, several fabricators have enjoyed improved RDR results by using a dual step DC plating current density. As an example, plate the first 45 minutes of the cycle at 10–12 amps per suqare foot (ASF), then ramp up to 20–25 ASF [9] . Filling Blind Vias and Through Holes with Non-conductive Materials OEMs and circuit board designers are also driving the use of via filling polymeric materi- als for blind, buried and in some cases through- holes. In addition, these formulations are of a non-conductive nature that provides a high quality plugged via, and is also cost effective. The requirements for these non-coductive via filling paste materials are: • Good adhesion between copper and paste even under temperature influences • Good adhesion of copper, dielectrics or photo resist • Solvent free, one pack system • No air inclusions in the paste • g > 140 °C • CTE < 40 ppm (below T g ) • No shrinkage during curing • Easily planarized A 100% solids content of the paste material with the thermally cross-linkable epoxy resin and specially designed ceramic fillers ensures a low coefficient of thermal expansion. Interest- ingly, the coefficient of thermal expansion must remain in the 40–60 ppm range in order to en- sure that no cracking occur in the filled via. In addition, it is critical that Z-axis expansion be minimized in order to prevent the plated cap from lifting (Figure 10). Half-etching Part and parcel to implemenation of HDI manaufacturing is the ability to provide finer lines and spaces. The issue here is that when subtractive etching is employed to define the circuitry, there is a signifcant risk of excessive undercut and loss of line width. Again this is LEAD-FREE REFLOW FOR HIGH-LAYER-COUNT PCBS continues Figure 8: superfilled and stacked vias. Figure 9: Via-in-pad overmetalized and filled via.