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42 SMT Magazine • December 2014 power and mixed signal integration with power and ground pins for different power domains. Also, PCB designers want passive components as close to a chip's power and ground pins as possible to improve decoupling. Finally, PCB technology is being driven to minimize chip-to- chip spacing in order to increase speed and sig- nal integrity. Increasing performance at a lower cost drives demand for BTC. These designs with tighter chip and component spacing however, present challenges if rework is required. Tier 1 OEMs have increasingly turned to ver- tically integrated EMS providers to develop the technologies needed to bring complex, high- performance products to market. Some of the key technology challenges OEMS and EMS pro- viders are working to solve include: minimiz- ing voids in BTCs; reducing the pitch between components while reserving sufficient space for rework; eliminating head-on-pillow defects in connections; and improving the robustness of PCBs used in high-temperature and/or corrosive industrial environments such as oil and gas ex- ploration. These issues continue to drive extraordinary advances in SMT processes as the number of terminations increase and pad pitch decreases. Here is a review of some SMT technology ad- vances in 2014 and a look ahead to the chal- lenges in 2015. challenge No. 1: reducing voiding In bTcs PCBs with BTCs are increasingly common, as BTCs have the advantage of offering good performance—both in signal integrity and ther- mal performance—at a relatively low cost. How- ever, increasing pin count and package size and reduced pitch on BTCs creates production chal- lenges. The increased pin count allows more functionality, and manufacturing faces new challenges in producing reliable contacts with these large-surface-area devices. The biggest challenge with BTC packages is thermal pad voiding. During the solder reflow process, chemicals or air can be trapped in the solder, creating voids that may impact thermal conductivity or solder joint reliability. Large voids can result in early product failures or long term reliability risks. Thermal pads present a unique challenge during reflow, as the pads are typically larger and connected to large copper areas within the PCB, and therefore taking lon- ger to reflow than solder balls associated with signal pads. As we enter 2015, stencil design techniques, soldering materials, new processes and design for manufacturability practices are continuing efforts being practiced and fine-tuned to mini- mize voiding, while vacuum reflow is also being investigated with promising results. challenge No. 2: rework challenges rise as component Spacing decreases OEMs are focused on functionality and per- formance. The use of decoupling capacitors for noise reduction leads to designs with more interconnects and smaller components with tighter component spacing. New designs, with more demanding signal integrity requirements can result in conflicts between layout require- ments and what can be manufactured. With the conflicts between design require- ments and process capability, rework is becom- ing a challenge. For some high-performance FEATurE SUrFAce mOUNT TecHNOLOGY AdvANcemeNTS IN 2015 continues Figure 2: pCB for high-density BgA, with 2597 connections, in production today.