Design007 Magazine

42 The PCB Design Magazine • October 2015 If power planes are used as reference planes, then the return current must transverse stitch- ing capacitors in order to jump between ground and power planes. The current flowing through these stitching capacitors will create a voltage drop across them. These voltages may radiate adding to system noise problems. Determining the required layer count: the number one question! Over the years, a number of people have put forward equations to determine the route den- sity. Rent's Rule is one such model. where: n is the number of nets X and Y are the board width and length in inches M is the number of routing layers Good luck getting any serious results from such equations. There are just too many vari- ables to take such a basic approach to layer count determination. This is my line of attack: As with Rent's Rule, I start with the route pitch. Technology rules are based on the minimum pitch of the SMT components employed and are basically the largest trace, clearance and via allowable whilst minimiz- ing PCB fabrication costs. Technology of 4/4 mil (trace/clearance) and vias of 18/8 mil (pad/hole) are generally required for com- plex high-speed designs incorporating BGAs. However, if you can use less demanding di- mensions, then this will reduce cost and im- prove fabrication yield. Once these rules have been established, calculate the stackup required for the desired characteristic impedance (Zo) and the differ- ential impedance (Zdiff) as per the component datasheets. Generally, 50/100 ohm Zo/Zdiff are used. Keep in mind that lower impedance will increase the dI/dt and dramatically increase the current drawn (not good for the PDN). While higher impedance will emit more EMI and also make the design more susceptible to outside in- terference. So, a good range of Zo, for a digital design, is 50–60 ohms. The total number of layers required for a given design is dependent on the complexity of the design. Factors include: • The number of signal nets that must break out from a BGA. • The number of power supplies required by the BGAs. beyond design STACKuP PLANNING, PART 4 Figure 1: A 10-layer configuration using nelco n4000-13 2.5ghz material.

• Cover
• Feature Articles — Accelerating the PCB Design Cycle
• Table of Contents
• Column — Squeezing Seconds Out of the Design Cycle
• Feature — Don't Be Held Hostage by Design Cycle Time
• Short — Whelen Engineering: The First New Captive in Decades?
• Feature — Accelerating the Design Cycle: Moving from Discipline-Centric to Product-Centric Design
• Short — Discovery about New Battery Overturns Decades of False Assumptions
• Feature — The Readers Speak: Tips on Accelerating Your Design Cycle
• Short — Superconductivity Trained to Promote Magnetization
• PCB007 Highlights
• Feature Column — Speeding up the Design Cycle: 10 Things to Remember
• Column — Stackup Planning, Part 4
• Short — Big Range of Behaviors for Tiny Graphene Pores
• Column — Avoiding the Black Spot of Negative Expectations
• Short — Back to the Future: Science Fiction Turns Science Fact
• Column — Impact of Final Plated Finish on PCB Loss
• Short — How Leaky is Your Device?
• MilAero007 Highlights
• Article — The Gerber Guide, Chapter 3
• Article — Analyzing Condensation and Evaporation in Headlights with Thermal Simulation
• Short — Energy Out of Thin Air
• Top Ten Recent Highlights from PCBDesign007
• Events Calendar
• Advertiser Index and Masthead