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October 2015 • The PCB Design Magazine 43 • The component density and package types. • If there are BGAs of 0.8 mm or less, plated-through-hole (PTH) vias will impede the routing. • Also, with high layer count boards, the via aspect ratio will increase the diameter of the vias. Via length to hole aspect ratio should be less than 8:1 or the reliability will decline significantly. In this case, a combination of PTH and blind and buried vias may be required. Experienced PCB designers get a feel for it after a while, but a good way to check if you have enough layers is to autoroute the board. With no tweaking, the autorouter needs to com- plete at least 85% of the routes to indicate the selected stackup is routable. The performance of the autorouter also impacts on the completion rate. You may have to re-evaluate the place- ment a couple of times to get the best results. In general, eight layers is a good starting point for DDR type designs. Remember, it is much easier to increase the number of layers than to reduce them, so start with the minimum. 10-Layer Stackup A 10-layer board is similar to an eight-layer with the addition of two more embedded signal layers. These are used to increase routability and to add planar capacitance. I have used Nelco N4000-13 2.5GHz material (Figure 1). This is another common high-speed material. The stackup accommodates 50/100 ohm digital, 40/80 ohm DDR3 and 90 ohm USB. Also, I have a combination of PTH and blind and buried vias with appropriate aspect ratios for a total board thickness of 60.82 mils. In this case, internal beyond design layers 3, 4, 7 and 8 can be used for the DDR3 routing as three of these layers are referenced to GND whilst the other (layer 7) is referenced to the 1.5V DDR3 PDN (or 1.35V in the case of lower power devices). The layer 7 power plane can have a 1.5V island directly above the DDR3 devices. With a 4.32 mil dielectric between the planes, there is also excellent planar capacitance of about 240 pF/in 2 . This will reduce the AC im- pedance of the DDR3 PDN at frequencies about 1GHz which is required for this type of design. The outer microstrip layers should not be used for routing—except for fanout. Apart from the fact that outer layers radiate more than internal layers, they also vary considerably in impedance. This is due the uneven plating thickness of the final electrolysis process used to plate the though-hole barrels during fabrica- tion. Blind vias can be used to fanout from the BGA and drop directly to either GND or layer 3. The PTH could be used to transverse the signals to the other layers or alternatively a buried via could be used. Figure 2 illustrates an alternative of buildup microstrip (outer layers). In this case, layer 1 is only used for fanout to layer 2, GND or Power. But layer 2 can be used for high-speed rout- ing of SERDES or other differential signals. It is closely coupled to the layer 3 (GND plane) and will have constant impedance. 12-Plus Layout Count I could go on and describe each successive layer count in detail, but I'm sure you get the drift by now. Figure 3 illustrates the signal/ plane configuration for 12–18 layers. There are of course, many variations that could be em- ployed depending on the application. The ICD Stackup Planner has default stackups from 2–18 STACKuP PLANNING, PART 4 Figure 2: Buildup microstrip layers.