Issue link: https://iconnect007.uberflip.com/i/615135
44 The PCB Design Magazine • December 2015 In the dark ages of power distribution de- sign, the typical advice was to use a bulk capac- itor and one 0.1uF bypass capacitor for every power pin on the digital circuit. This was very unscientific, but served the industry reasonably well in low-density and low-speed circuits. As the designs got more demanding, the target impedance concept was developed [1] . Using a target impedance, designers had a metric and a design goal to guarantee that the voltage tran- sients stay within specified limits. Strictly speaking, the target-impedance con- cept is valid only for flat self-impedance pro- files; however, most of our practical designs do not have that luxury. With non-flat impedance profiles, the noise is different. Surprisingly and counterintuitively, keeping the same maximum impedance, the more we deviate from the flat impedance by pushing the impedance down in certain frequency ranges, the higher the worst- case transient noise becomes. This raises the question how to do a systematic design and also gives rise to speculations about rogue waves [2] . But there is a systematic, fast and efficient way of calculating the worst-case noise for any arbi- trary impedance profile. The target impedance concept assumes that the power distribution network is hit by a se- ries of current steps, each current step having a magnitude of DI and fastest transition time of t tr . If up to the BW bandwidth of the excitation the PDN impedance is Z target , the resulting volt- age transients are within the DV limits. column by Istvan Novak oRACle QUIET PoWER Systematic Estimation of Worst-Case PDN Noise: Target Impedance and Rogue Waves