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66 The PCB Design Magazine • December 2015 ple for system-level SI simulation. The "info" qualifier implies an Internet connection, which might be provided by another subsystem and accessed via a high-speed Ethernet connection or might be implemented by an RF section of the PCB. In either case, it adds significantly to the complexity of the board. The chipset re- quired to decode and process HD video and audio are high-speed, high-pin-count devices, usually requiring a fairly complex board. On-board memory is required with its asso- ciated multibyte parallel bus, thereby indicating the need for controlled impedance and delay- tuned signal routing during physical design as well as timing analysis for performance signoff. The remote passenger displays require a simi- lar level of decoding capability and might be nearly as complex as the in-dash PCB. They also require a high-speed multi-drop interface, such as Ethernet, be available on both the in-dash and remote boards. The design requirements for such systems include complex multi-layer boards and high-speed parallel bus routing, as well as high-speed serial interconnect with mul- tiple boards. Designs must be simulated and analyzed including full serial channel charac- terization. These challenges for physical design and SI simulation are not unique to automotive applications and are available with enterprise- class PCB physical design software. First consider routing and performance veri- fication of the high-speed memory buses. There are five key aspects of PCB design software for high-speed parallel bus design: (1) constraint- based physical design, (2) automation for bus routing, (3) initial timing enforcement, (4) board-level SI performance assessment and (5) power-aware SI compliance signoff. Constraint- based physical design enables a correct-by- construction flow. Physical as well as electrical constrains are dynamically flagged as routing occurs for instant feedback and on-the-fly cor- rection. The alternative is a much more time- consuming process of iteratively cleaning-up design rule check (DRC) errors after initial PCB routing is completed. Autorouting is critically important and available for individual nets, differential pairs and entire buses. A bit of in- teractive guidance for the autorouter, a process dubbed "auto-interactive," during device-local breakout routing and bus-level delay tuning greatly speeds these tasks. The electrical param- eters of impedance and delay are computed in real time whether routing is performed manu- ally or automatically. These per-net electrical parameters are available to support timing anal- ysis and rapid interactive tuning of the entire bus to comply with standard protocols (e.g., DDR3, DDR4). These tasks are all accomplished by a layout designer before the final completed board design is passed to an SI engineer for per- formance verification. PCB design team members first assess the design for operating condition independent characteristics, such as net impedance, cou- pling among nets and return path discontinui- ties. The analysis is rapid and very high capac- ity, enabling the entire board to be considered. The results are available in tables or as color- shaded layout overlays for intuitive assessment. A power-aware analysis (including the effects of the actual current return paths in the PDN) might be performed to narrow down SI issues to individual byte lanes or even a few nets. This rapid assessment applies ideal I/O buffers with piecewise linear signals and examines a small set of SI metrics defined by received signal, far- end crosstalk and intersymbol interference. SI issues with routing are quickly and reli- ably identified to be addressed in layout or ex- amined further with more detailed SI simula- tion. Layout-based detailed simulations of a few nets might be performed relatively quickly to judge performance or validate the performance improvement of design changes. Whole-bus ELECTRICAL DESIGN CHALLENGES FoR AUToMoTIVE PCBS " The chipset required to decode and process hD video and audio are high-speed, high-pin-count devices, usually requiring a fairly complex board. " article