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36 SMT Magazine • March 2016 increasing the chances of testing at the lead and not the pad. This should be avoided due to the risk of damaging the component. Also the cus- tomers need to be open minded about "witness marks" left behind by the tester. Harder sol- der—for example lead-free—reduces this prob- lem. Testing this technology typically results in higher test coverage approaching 100%. Higher-technology product can pose a much more significant challenge. The technology in this class includes high-speed digital, via in pad, blind buried vias and high BGA count. The curveball in this case is the number of circuits that actually never see an external via, making it impossible to probe the circuit. The previous advice still applies: Try to have a via exposed for every circuit. This includes making sure they are not covered by a component or soldermask. Test coverage can be enhanced if the engineer allows all exposed vias to be unmasked. This ap- proach will give the test engineer options to test the circuit; solving common problems like test- ing around tall components. Typically, this re- sults in "okay" test coverage, but no one wants to be just okay! Superior test coverage on this type of prod- uct includes the use of boundary scan (JTAG) technology to significantly increase the test coverage as well as reduce test time. Stating the obvious, this presumes that the components on the board are boundary scan capable. Assuming this is the case, the five signal boundary scan daisy chain circuit needs to be connected. Gen- erally, the electrical engineer connects them, but not for test purposes. Instead it is seen as a method for programming components. It is important to note that the original intent of boundary scan was to test and not program; however, it is used more often for programming. Implementing boundary scan for test can be no different than your current programming routine. Simply connecting the chain opens up the possibility of test, and is a great beginning but only the beginning. It is recommended that a test engineer who specializes in boundary scan test review the schematic before layout be- gins. Doing so typically will yield a faster, more thorough test. Test throughput also increases by removing all circuits tested at boundary scan from the flying probe test program. This approach has been used on boards with more than 35,000 test points, which resulted in 95% test coverage. So the challenge has been met. It is pos- sible to have a highly tested product built in the United States at an affordable price. Amaz- ingly, what has been outlined here requires less upfront and design work than the traditional bed of nails in-circuit test and can be used in all phases of development, including prototype, pilot and production runs. SmT W. Scott Fillebrown is the chief Technology officer of libra Industries Inc. dESIgn for tESt In thE u.S. MarkEt Scientists at the University of Southampton have made a major step forward in the development of digital data storage that is capable of surviving for billions of years. Using nanostructured glass, scientists from the University's optoelectronics research Centre (orC) have developed the recording and retrieval process- es of five dimensional (5D) digital data by femtosec- ond laser writing. The storage allows unprecedented properties including 360 TB/disc data capacity, thermal sta- bility up to 1,000°C and virtually unlimited lifetime at room temperature (13.8 billion years at 190°C) opening a new era of eternal data archiving. As a very stable and safe form of portable memory, the technology could be highly useful for organizations with big archives, such as national archives, muse- ums and libraries, to preserve their information and records. The researchers are now looking for industry partners to further develop and commercialize this ground-breaking new technology. Eternal 5D Data Storage Could Record the History of Humankind