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24 The PCB Design Magazine • March 2016 We should not only consider the engineering time but also the cost of delaying the products market launch. This missed opportunity could cost your company hundreds of thousands of dollars, if not the total loss of market share. In a previous column, Introduction to Board-Level Simulation and the PCB Design Process, I mentioned that the cost of develop- ment is dramatically reduced if simulation is employed during the design cycle. The design changes that occur early in the design process are less expensive compared to those that take place after it is introduced into full-scale pro- duction. The cost of the change increases with development time. Fundamentally, the design changes can be classified into pre-production and post-produc- tion modifications. The pre-production changes can happen in the conceptual, design, proto- type, or the testing stage. The post-production stage change will happen almost immediately when the product is introduced into produc- tion or worse still, be recognized only when the product reaches the market. The later the stage, the more expensive the issue is to fix. The ad- vantage of virtual prototyping is that it iden- tifies issues early in the design process so they can be rectified before they become a major problem. For years, entry-level tools allowed us to quickly design and build a prototype, some of these based on chip vendor reference designs. Unfortunately, those days are long gone and development teams are finding that they need to employ analysis tools to verify their design before release. One cannot rely on reference de- signs to actually work in the operating environ- ment. These designs are generally built by R&D teams who have high academic qualifications but little appreciation of design for reliability or manufacturability—the real world. This in-circuit design, find-and-fix meth- odology is imperative in today's design envi- ronment, where multiple fast rise-time signals propagate at faster and faster speeds with the implementation of each new technology. We no the need for speed: strategies for design efficiency Figure 2: Constraints planning at the schematic level.

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