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38 The PCB Design Magazine • July 2016 cutable software modules, which can model the types of adaptive equalization commonly used today, such as continuous time linear equal- ization (CTLE), decision feedback equalization (DFE), and feed forward equalization (FFE). While IBIS-AMI models are much more read- ily available for SerDes devices than just a few years ago, there may still be situations where an IBIS-AMI model is not available for a specific de- vice, but you know the general characteristics of its equalization, such as the number of FFE taps or the CTLE frequency response. In these cases, today's tools enable you to quickly synthesize the IBIS-AMI model you need to carry out the simu- lation, and simulate your system-level interface. With appropriate interconnect and device models in place, you can get down to the busi- ness of verifying compliance for your critical high speed interfaces. For DDR interfaces, the landscape is changing. Starting with DDR4, memory interfaces are starting to adopt serial link modeling and analysis techniques. Memo- ry controllers now have the FFE and CTLE tech- niques that serial links have had for many years, and because of that, are beginning to use IBIS- AMI models as well. In addition to device mod- eling, we now see standards like DDR4 moving from a traditional setup and hold time compli- ance approach to a mask-based one, like those historically seen for serial links, along with spe- cific BER requirements. Checking compliance for signal quality and mask adherence for entire memory interfaces full of signals (and even multiple interfaces in Figure 9: Serial link analysis including equalization from IBIS-AMI models. SIGNAL INTEGRITY TOOLS AND DESIGN METHODOLOGY IN THE MODERN AGE