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July 2016 • The PCB Design Magazine 39 a design) can be very time-consuming, so good automation of waveform post- processing is essential, along with gen- eration of detailed sign-off reports. In addition to the mask-based com- pliance checking above, serial link com- pliance will often have other unique re- quirements for the interface, including specific frequency domain characteris- tics for the interconnect. In summary, thorough verification flows from good pre-layout analysis. Simulation test benches used up front can be re-used and updated with de- tailed interconnect models extracted from layout. Different types of EM solv- ers are needed to perform power-aware bus extraction for DDR interfaces, and intelligent deployment of full-wave techniques is needed to efficiently char- acterize layer transitions for high data rate serial link interfaces. Automated, interface-specific compliance analysis needs to be applied to the final design, allowing you to sign off your design to fabrication with confidence, and help achieve first-pass success in the lab. Figure 10: Mask-based compliance for DDR4 signals. Figure 11: PCI Express Gen 3 compliance criteria. SIGNAL INTEGRITY TOOLS AND DESIGN METHODOLOGY IN THE MODERN AGE