Issue link: https://iconnect007.uberflip.com/i/994883
JUNE 2018 I DESIGN007 MAGAZINE 27 with routing complexity in both vertical direc- tions such as PoP, SiP, chip-scale packaging and 3D-IC/3D packaging. The new tools also automate routing of the chip RDL and package escape, reducing pathfinding cycle time and making it possible to optimize die bump place- ment. The new approach makes it possible to study the trade-offs involved in using different numbers of package layers while simultane- ously considering RDL routing on the IC side and the escape route on the PCB side in a single design view. Advantages of the new approach include lower RDL, interposer/substrate and package layer count, improved signal integrity and faster time-to-market. Each person working on the project can see their piece of the puzzle in the context of the full product, making it easier to optimize pin assignments and avoid connectivity errors. For example, package/IC bump assignment can be performed while viewing the effects on the rats nest at the PCB level. The designer can observe the potential impact at the package and IC level of making automatic or interactive pin swaps at the board level to improve PCB routability. The pin swap operation is automatically com- municated between the package and PCB data- bases, eliminating the need for CSV or other neutral files to communicate the change. Mul- tiple engineers can work simultaneously on a single substrate because the tool enables engi- neers to lock the package design. If a designer needs to make a pin swap in a locked package design, they can send a notification that the other engineers can accept or reject as an ECO. Simulation The effects of changes from a signal integrity, power integrity or thermal point of view can be determined by performing multidiscipline, multi-physics analysis with solutions from pro- viders such as Keysight Technologies, ANSYS, AWR, CST and Synopsys. The co-design envi- ronment enables signal traceability across the complete system. Signal paths can be reviewed and analyzed as they cross design and compo- nent boundaries from drivers through the sys- tem interconnect to receivers. Intelligent and integrated schematic- or layout-based simu- lation environments support multiple design flows. Conclusion The move from coplanar designs to complex 3D stacked structures and embedded devices is driving the need for tools that can accurately render and provide meaningful visual and DRC feedback to enable, rapid right-the-first-time Figure 5: Co-design environment for chip, package, and board in 3D.