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42 DESIGN007 MAGAZINE I JUNE 2018 Whereas parallel (end termination), is pre- ferred for busses with a number of loads in a multi-drop topology. For DDR3/4 layouts, a series termination is generally not required for on-board memory devices. However, if your design has plug-in memory then the data and data mask signal length may be excessive and require a series termination. With the fly-by address, control and com- mand (ACC) signals, the traces should be routed as practicable as possible to the mem- ory device pins and the parallel termination placed at the end of the line as in Figure 1. Short stubs can be used to connect the passing signal to each memory device in sequence but the longer the stubs the higher the capacitance. This stub capacitance, along with the parasitic input capacitance of the receiver pin, creates an imperfection in the termination network. When implementing parallel terminations, it is not always possible to place the termination after the final load in a multi-drop topology due to real estate restrictions. Figure 2 shows the schematic of this configuration. If the stub is very short and the signal edge rate is not excessively fast, then this may be acceptable. However, as the edge rate increases, the extra capacitance of the stub is significant and cre- ates reflections. When the first incident wave arrives from the driver, part of that wave, which is a small pulse, bounces off the imperfection and returns to the driver. This pulse bounces again off the low-output impedance driver and returns one round trip later to the receiver. What we observe at the receiver is the initial rising edge, followed one round trip later by a secondary pulse. If the initial reflected pulse is sufficiently Figure 2: DDR3 address signal with termination before final load (all simulations performed in HyperLynx).